Patents by Inventor Yu-Jen Yen
Yu-Jen Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117342Abstract: An construction method of an embryonic chromosome signal library is provided. The construction method comprises obtaining an embryo and performing whole-genome amplification and next-generation sequencing to obtain a first chromosome signal; mapping the first chromosome signal to a chromosome reference signal to obtain a second chromosome signal; dividing the second chromosome signal within a predetermined interval range to obtain a third chromosome signal; and performing a regression correction on the sequencing read count (RC) of the third chromosome signal to obtain an embryonic chromosome signal library. Furthermore, a detection method and system of embryonic chromosomes are also provided. Thereby, the information comparison of the embryo chromosome signal library is used to determine whether the pre-implantation embryo is abnormal or not to achieve pre-implantation chromosome screening of pre-implantation embryos.Type: ApplicationFiled: October 2, 2023Publication date: April 11, 2024Inventors: LI-JEN SU, SHAO-PING WENG, YU-YU YEN, LI-CHING WU, HUI-YIN CHIU, JUI-HUNG KAO
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Publication number: 20240082861Abstract: A foam spray can includes a motor pump, a foaming tube, a can body, a cover body and a quick release structure. One end of the foaming tube is connected to the motor pump. The can body contains liquid. The cover covers an opening of the can body. The quick release structure includes a first and a second engaging structures disposed on the cover body and the can body, respectively. The first engaging structure can be engaged with the second engaging structure along a first direction. The first engaging structure can be separated from the second engaging structure in a moving distance less than a half circumference of the opening of the can body along a second direction opposite to the first direction. Therefore, the cover body and the cover body of the foam spray can be quickly assembled and disassembled.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Inventors: LIN-HAN YEN, YU-JEN FANG
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Publication number: 20240082980Abstract: A grinding device includes a waist-buckled device, a waxing/polishing device and a power cord. One of terminals of the power cord is connected to the waist-buckled device, and the other one of the terminals of the power cord is connected to the waxing/polishing device. The waist-buckled device includes an electric control board and a battery pack. The electronic control board is connected to the battery pack. Thus, it is convenient for the user to save the user's time and improve the efficiency of polishing works so that the machine in long time use can be achieved.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Inventors: LIN-HAN YEN, YU-JEN FANG
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Patent number: 10818208Abstract: A source driver includes a first output pad, a second output pad, a first charge-sharing path, a second charge-sharing path, a first charge-sharing switch, a second charge-sharing switch and a test circuit. A first terminal and a second terminal of the first charge-sharing switch are respectively coupled to the first output pad and the first charge-sharing path. A first terminal and a second terminal of the second charge-sharing switch are respectively coupled to the second output pad and the second charge-sharing path. The test circuit is coupled to the first charge-sharing path and the second charge-sharing path. The test circuit performs a test for the first output pad and the second output pad via the first charge-sharing path, the second charge-sharing path, the first charge-sharing switch and the second charge-sharing switch in a test period.Type: GrantFiled: September 14, 2018Date of Patent: October 27, 2020Assignee: Novatek Microelectronics Corp.Inventor: Yu-Jen Yen
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Publication number: 20200333817Abstract: An output stage circuit of a voltage regulator includes a first output transistor, a first voltage generator and a first stack transistor. The first stack transistor is coupled between the first output transistor and an output terminal of the voltage regulator, and includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the output terminal of the voltage regulator. The second terminal is coupled to the first output transistor. The third terminal is coupled to the first voltage generator.Type: ApplicationFiled: April 16, 2019Publication date: October 22, 2020Inventors: Chung-Jui Wu, Yu-Jen Yen
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Patent number: 10795392Abstract: An output stage circuit of a voltage regulator includes a first output transistor, a first voltage generator and a first stack transistor. The first stack transistor is coupled between the first output transistor and an output terminal of the voltage regulator, and includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the output terminal of the voltage regulator. The second terminal is coupled to the first output transistor. The third terminal is coupled to the first voltage generator.Type: GrantFiled: April 16, 2019Date of Patent: October 6, 2020Assignee: NOVATEK Microelectronics Corp.Inventors: Chung-Jui Wu, Yu-Jen Yen
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Publication number: 20200090563Abstract: A source driver includes a first output pad, a second output pad, a first charge-sharing path, a second charge-sharing path, a first charge-sharing switch, a second charge-sharing switch and a test circuit. A first terminal and a second terminal of the first charge-sharing switch are respectively coupled to the first output pad and the first charge-sharing path. A first terminal and a second terminal of the second charge-sharing switch are respectively coupled to the second output pad and the second charge-sharing path. The test circuit is coupled to the first charge-sharing path and the second charge-sharing path. The test circuit performs a test for the first output pad and the second output pad via the first charge-sharing path, the second charge-sharing path, the first charge-sharing switch and the second charge-sharing switch in a test period.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Applicant: Novatek Microelectronics Corp.Inventor: Yu-Jen Yen
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Patent number: 9041703Abstract: A source driver applied in a liquid crystal display is disclosed. The source driver at least includes a first pair of channels, a second pair of channels, two P-type digital/analog converting modules, two N-type digital/analog converting modules, two multiplexers, two polarization multiplexers, and four amplifying and buffer modules. The first pair of channels includes a first channel and a second channel which are adjacent, and the second pair of channels includes a third channel and a four channel which are adjacent. The two P-type digital/analog converting modules correspond to a first set of gamma values, and the two N-type digital/analog converting modules correspond to a second set of gamma values. The first pair of channels shares the two P-type digital/analog converting modules and the second pair of channels shares the two N-type digital/analog converting modules to save the used chip area.Type: GrantFiled: March 11, 2013Date of Patent: May 26, 2015Assignee: Raydium Semiconductor CorporationInventor: Yu-Jen Yen
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Patent number: 8866801Abstract: The present invention discloses a device with an automatic de-skew capability, comprising a data signal delay module, a plurality of data registers, and a delay data signal selection module. The present device outputs an optimal delay data signal and a clock signal to a source driver to drive a display panel.Type: GrantFiled: July 31, 2012Date of Patent: October 21, 2014Assignee: Raydium Semiconductor CorporationInventor: Yu Jen Yen
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Patent number: 8766690Abstract: A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.Type: GrantFiled: August 6, 2012Date of Patent: July 1, 2014Assignee: Raydium Semiconductor CorporationInventor: Yu Jen Yen
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Patent number: 8704814Abstract: A driving device and a driving method of a flat panel display are provided. The driving device includes a driving circuit, an output buffer and a buffer control module. The driving circuit outputs a pixel data during a valid data period, and an input terminal of the output buffer receives the output of the driving circuit. The buffer control module turns off the output buffer during a blanking data period, and turns on the output buffer during the valid data period in order to reduce power consumption of the output buffer, and maintain an image quality of the flat panel display.Type: GrantFiled: August 5, 2010Date of Patent: April 22, 2014Assignee: Himax Technologies LimitedInventor: Yu-Jen Yen
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Publication number: 20130235007Abstract: A source driver applied in a liquid crystal display is disclosed. The source driver at least includes a first pair of channels, a second pair of channels, two P-type digital/analog converting modules, two N-type digital/analog converting modules, two multiplexers, two polarization multiplexers, and four amplifying and buffer modules. The first pair of channels includes a first channel and a second channel which are adjacent, and the second pair of channels includes a third channel and a four channel which are adjacent. The two P-type digital/analog converting modules correspond to a first set of gamma values, and the two N-type digital/analog converting modules correspond to a second set of gamma values. The first pair of channels shares the two P-type digital/analog converting modules and the second pair of channels shares the two N-type digital/analog converting modules to save the used chip area.Type: ApplicationFiled: March 11, 2013Publication date: September 12, 2013Applicant: RAYDIUM SEMICONDUCTOR CORPORATIONInventor: Yu-Jen Yen
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Patent number: 8466908Abstract: A driving device and a driving method for dynamic bias are provided. The driving device includes a buffer and a bias control unit. An input terminal of the buffer receives a data voltage, and an output terminal of the buffer is connected to a load through a switch. The bias control unit connected to the buffer controls a bias of the buffer dynamically. During a transition period of the data voltage, the bias control unit controls the buffer in a normal bias state. During a power-saving period, the bias control unit controls the buffer in a low bias state, and controls the buffer in the normal bias state during a turning-off period of the switch. The driving device controls the buffer to sustain data voltage quickly during the turning-off period of the switch, so as to avoid the data voltage received by the load having errors and reduce power consumption.Type: GrantFiled: July 13, 2010Date of Patent: June 18, 2013Assignee: Himax Technologies LimitedInventor: Yu-Jen Yen
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Publication number: 20130038582Abstract: The present invention discloses a device with an automatic de-skew capability, comprising a data signal delay module, a plurality of data registers, and a delay data signal selection module. The present device outputs an optimal delay data signal and a clock signal to a source driver to drive a display panel.Type: ApplicationFiled: July 31, 2012Publication date: February 14, 2013Applicant: RAYDIUM SEMICONDUCTOR CORPORATIONInventor: YU JEN YEN
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Publication number: 20130038367Abstract: A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.Type: ApplicationFiled: August 6, 2012Publication date: February 14, 2013Applicant: RAYDIUM SEMICONDUCTOR CORPORATIONInventor: YU JEN YEN
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Patent number: 8279155Abstract: A source driver includes a receiver for receiving a digital signal at an input node to generate a received signal at an output node, and the receiver includes a first switch, a second switch, a voltage-limiting circuit and a channel. The first switch is utilized for selectively connecting the output node of the receiver to a first reference voltage based on the digital signal. The second switch is utilized for selectively connecting the output node of the receiver to a second reference voltage based on the digital signal. The voltage-limiting circuit is coupled between the input node and the output node of the receiver, and is utilized for limiting a voltage level of the input node of the receiver. The channel is utilized for generating a driving voltage based on the received signal.Type: GrantFiled: May 11, 2009Date of Patent: October 2, 2012Assignee: Himax Technologies LimitedInventor: Yu-Jen Yen
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Patent number: 8212758Abstract: A source driver includes a receiver for receiving a digital signal at an input node to generate an output signal at an output node, where the receiver includes a first switch, a second switch, a voltage-limiting circuit, a third switch and a channel. The first switch is for selectively connecting the output node of the receiver to a first reference voltage based on the digital signal. The second switch is for selectively connecting the output node of the receiver to a second reference voltage based on the digital signal. The voltage-limiting circuit is coupled between the input node and the output node of the receiver, and is for limiting a voltage level of the input node of the receiver. The third switch is coupled between the voltage-limiting circuit and the output node of the receiver. The channel is for generating a driving voltage based on the output signal.Type: GrantFiled: December 2, 2009Date of Patent: July 3, 2012Assignee: Himax Technologies LimitedInventor: Yu-Jen Yen
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Publication number: 20120032935Abstract: A driving device and a driving method of a flat panel display are provided. The driving device includes a driving circuit, an output buffer and a buffer control module. The driving circuit outputs a pixel data during a valid data period, and an input terminal of the output buffer receives the output of the driving circuit. The buffer control module turns off the output buffer during a blanking data period, and turns on the output buffer during the valid data period in order to reduce power consumption of the output buffer, and maintain an image quality of the flat panel display.Type: ApplicationFiled: August 5, 2010Publication date: February 9, 2012Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Yu-Jen Yen
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Publication number: 20120013587Abstract: A driving device and a driving method for dynamic bias are provided. The driving device includes a buffer and a bias control unit. An input terminal of the buffer receives a data voltage, and an output terminal of the buffer is connected to a load through a switch. The bias control unit connected to the buffer controls a bias of the buffer dynamically. During a transition period of the data voltage, the bias control unit controls the buffer in a normal bias state. During a power-saving period, the bias control unit controls the buffer in a low bias state, and controls the buffer in the normal bias state during a turning-off period of the switch. The driving device controls the buffer to sustain data voltage quickly during the turning-off period of the switch, so as to avoid the data voltage received by the load having errors and reduce power consumption.Type: ApplicationFiled: July 13, 2010Publication date: January 19, 2012Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: YU-JEN YEN
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Publication number: 20110175898Abstract: A data insertion circuit of a display apparatus includes a signal source, a switch unit and a control unit. The signal source is for providing a video driving signal. The switch unit has an output node coupled to a channel of the display apparatus, a first input node coupled to the signal source, and a second input node coupled to a control voltage for data insertion, and is for selectively outputting the video driving signal or the control voltage to the output node. The control unit is coupled to the switch unit, wherein when the display apparatus is in a normal mode, the control unit controls the switch unit to transmit the video driving signal to the display apparatus; and when the display apparatus is in a data insertion mode, the control unit controls the switch unit to transmit the control voltage to the display apparatus.Type: ApplicationFiled: January 21, 2010Publication date: July 21, 2011Inventors: Yu-Jen Yen, Chien-Ru Chen