Abstract: The present invention discloses a display driver and related display. The display driver includes: a plurality of level shifters, respectively receiving input signals for outputting shifted signals; a plurality of switches; and a digital-to-analog converter, having a plurality of input terminals electrically connected to outputs of the level shifters respectively via the switches directly; wherein the switches are turned off while the level shifters are in a transition to convert the input signals into the shifted signals.

Abstract: The present invention discloses a driving module for driving an LCD panel and a method of forming an LCD device. The driving module includes: a source driving circuit, for driving the LCD panel; and a heat sink module, coupled to the source driving circuit and integrated with the LCD panel, for dissipating heat generated from the source driving circuit. The method of forming an LCD device including: utilizing a specific semiconductor process to form a LCD panel; and forming a heat sink module integrated with the LCD panel during the specific semiconductor process.

Abstract: The present invention discloses a level shift circuit and a control pulse shaping unit therewith. A level shift circuit for transition of a low-voltage input signal into a high-voltage output signal, the circuit comprising two pairs of transistors and a control unit. Two pairs of transistors, wherein the transistors in one of the pairs are both turned on in response to the input signal so that a voltage on a reference voltage node is coupled to a gate of one of the transistors in the other pair; a control unit decoupling a reference voltage from the reference voltage node during a first phase, and partially and fully coupling the reference voltage to the reference voltage node respectively during a second and third phases.

Abstract: A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.

Abstract: The present invention provides a source driver comprising a shift register, a line buffer for storing a data signal and outputting a buffered data signal, and a level shifter for generating a level-shifted data signal based on the buffered data signal. The line buffer further comprises a charge pump supplying a pumped voltage based on a voltage source and a buffer powered by the pumped voltage and outputting a buffered data signal based on the data signal.

Abstract: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus is used for shifting a level of a data signal. The level shifting apparatus comprises a first charge pump and a level shifter. The first charge pump supplies a first pumped voltage based on the data signal. The level shifter generates a level-shifted data signal based on the first pumped voltage.

Abstract: The present invention discloses a level shift circuit and a control pulse shaping unit therewith. A level shift circuit for transition of a low-voltage input signal into a high-voltage output signal, the circuit comprising two pairs of transistors and a control unit. Two pairs of transistors, wherein the transistors in one of the pairs are both turned on in response to the input signal so that a voltage on a reference voltage node is coupled to a gate of one of the transistors in the other pair; a control unit decoupling a reference voltage from the reference voltage node during a first phase, and partially and fully coupling the reference voltage to the reference voltage node respectively during a second and third phases.

Abstract: A level shift circuit with voltage pulling includes a voltage-pulling circuit and at least one inverter. The voltage-pulling circuit contains a capacitance element, a first switch receiving a first voltage and charging the capacitance element according to a first control signal, a second switch discharging the capacitance element and being able to generate a first input signal according to a second control signal, and a third switch receiving a second voltage and being able to generate the first input signal according to the first control signal. The at least one inverter conditions the first input signal and is coupled to the voltage-pulling circuit.

Abstract: A level shift circuit with a low-voltage input stage, converting an input signal to an output signal, includes at least one level shift unit. The level shift unit includes a first transistor receiving a supply voltage and a first gate control signal to generate a second gate control signal, a second transistor receiving the supply voltage and the second gate control signal to generate the first gate control signal, a third transistor receiving the input signal to ground the second gate control signal, a fourth transistor receiving an inverted signal of the input signal to ground the first gate control signal, a fifth transistor receiving a first control signal to transfer the second gate control signal to the third transistor, and a sixth transistor receiving the first control signal to transfer the first gate control signal to the fourth transistor. The level of the output signal is determined by that of the first control signal.

Abstract: A level shift circuit with voltage pulling includes a voltage-pulling circuit and at least one inverter. The voltage-pulling circuit contains a capacitance element, a first switch receiving a first voltage and charging the capacitance element according to a first control signal, a second switch discharging the capacitance element and being able to generate a first input signal according to a second control signal, and a third switch receiving a second voltage and being able to generate the first input signal according to the first control signal. The at least one inverter conditions the first input signal and is coupled to the voltage-pulling circuit.

Abstract: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus comprises a level shifter and an asynchronous dynamic control circuit. The level shifter has a first switch and connected to a high power supply voltage source via the first switch, wherein the level shifter shifts a level of an input signal and outputs an output signal if enabled. The asynchronous dynamic control circuit sends an enabling signal for temporarily turning on the first switch to enable the level shifter.

Abstract: The level shift circuit and the display using same are disclosed. The level shift circuit includes a shift logic circuit and a logic controller. The shift logic circuit is capable of shifting a level of an input signal. The logic controller is capable of resetting the shift logic circuit before the shift logic circuit shifting the level of the input signal, and then enabling the shift logic circuit to shift the level of the input signal.

Abstract: A level shift circuit for conversion of a low-voltage input signal into a high-voltage output signal is provided. The level shift circuit includes: two pairs of transistors, a control unit, and a charge-sharing unit. The transistors in one of the pairs are both turned on in response to the input signal so that a voltage on a reference voltage node is coupled to a gate of one of the transistors in the other pair. A control unit decouples and couples a first reference voltage from the reference voltage node during a first and second phases respectively. A charge-sharing unit is temporarily shorting for preventing failure of conversion.

Abstract: A latch-type level shift circuit comprises a first latch circuit and a second latch circuit. The first latch circuit is powered by an independent reference voltage and receives a differential pair of low voltage signals to generate a differential pair of intermediate signals. The second latch circuit is powered by an internal reference voltage and receives the differential pair of intermediate signals to generate a differential pair of high-voltage output signals. The first latch circuit of the latch-type level shift circuit replaces the inverters used in the conventional level shift circuit, and thus, the capability of changing the state of the latch-type level shift circuit is improved.

Abstract: The invention provides solutions to solve the power consumption of the image data buses of an LCD source driver. With a bus buffer provided in one embodiment of the invention, a first image data buses are divided into several groups. Each group of image data buses is dispatched by the bus buffer. It is possible in one embodiment of the invention that some groups are active when the others are passive. Therefore, unnecessary power consumption is cut off. Despite the power saved by the management of the bus buffer, the parasitic capacitance of each group of image data buses is much smaller than that of the image data buses in the prior art. Moreover, the management of the bus buffer can depend upon the layout patterns or the layout locations of circuit components so that the driving strength of the bus buffer may be modified according to the layout pattern or the layout locations.

Abstract: The invention provides solutions to solve the power consumption of the image data buses of an LCD source driver. With a bus buffer provided in one embodiment of the invention, a first image data buses are divided into several groups. Each group of image data buses is dispatched by the bus buffer. It is possible in one embodiment of the invention that some groups are active when the others are passive. Therefore, unnecessary power consumption is cut off. Despite the power saved by the management of the bus buffer, the parasitic capacitance of each group of image data buses is much smaller than that of the image data buses in the prior art. Moreover, the management of the bus buffer can depend upon the layout patterns or the layout locations of circuit components so that the driving strength of the bus buffer may be modified according to the layout pattern or the layout locations.

Abstract: An interface circuit for data transmission and the method thereof is described. The interface circuit includes a transmitter providing data through first data signals during the data periods corresponding to rising and falling edges of a clock signal, a transition detection unit selectively asserting a detection signal in response to the number of the first data signals having transitions between every two adjacent data periods, a transition reduction unit generating second data signals by outputting the inverted and non-inverted first data signals respectively when the detection signal is asserted and de-asserted, and a receiver restoring the data from the second data signals and the detection signal.

Abstract: An operational amplifier circuit includes an operational amplifier, a bias current provider, and a control circuitry. The operational amplifier drives a load according to an input signal. The bias current provider is coupled to the operational amplifier and provides a bias current to the operational amplifier. The control circuitry is coupled to the bias current provider and controls the bias current provider to adjust the bias current according to an operating status of the operational amplifier circuit.

Abstract: An operational amplifier circuit includes an operational amplifier, an intermediate circuitry, and a control circuitry. The intermediate circuitry is coupled to a load. The operational amplifier is coupled to the intermediate circuitry and drives the load through the intermediate circuitry according to an input signal. The control circuitry is coupled to the intermediate circuitry and controls the intermediate circuitry to adjust an equivalent loading induced by the intermediate circuitry.

Abstract: A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.