Patents by Inventor Yu-Jui Chang

Yu-Jui Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121106
    Abstract: In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Chia-Wei Wang, Hui-Jung Tsai, Yu-Tzu Chang
  • Patent number: 11106282
    Abstract: A mobile device includes sensors and a processor. The sensors are disposed on opposite edges of the mobile device respectively. The processor is configured to collect a first data set labeled with a right hand holding gesture, collect a second data set labeled with a left hand holding gesture, establish a determination model associated with the first data set and the second data set, and in response to the processor collects a third data set comprising the holding positions and the force values detected by the sensor, determine a current holding gesture according to the third data set in reference to the determination model.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 31, 2021
    Assignee: HTC Corporation
    Inventors: Yu-Kai Hung, I-Jui Chang, Jhao-Yin Li, Wen-Yu Weng, Yu-Ta Chen
  • Patent number: 11074874
    Abstract: An electro-phoretic display apparatus including an electro-phoretic display panel and a driving circuit is provided. The electro-phoretic display panel includes a display area and a border area. The driving circuit is configured to drive the display area to display an image frame according to a first voltage. The driving circuit drives the border area to maintain displaying a border of a first color or a second color according to a second voltage. The driving circuit generates the second voltage according to the first voltage. The border area includes electro-phoretic particles of the first color or the second color. A voltage difference between the first voltage and the second voltage drives the electro-phoretic particles of the first color or the second color to be maintained to a predetermined position such that the border area maintains displaying the border of the first color or the second color.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 27, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Hao-Ting Hsu, Chia-Hao Kuo, Yu-Jui Chang
  • Publication number: 20200279535
    Abstract: An electro-phoretic display apparatus including an electro-phoretic display panel and a driving circuit is provided. The electro-phoretic display panel includes a display area and a border area. The driving circuit is configured to drive the display area to display an image frame according to a first voltage. The driving circuit drives the border area to maintain displaying a border of a first color or a second color according to a second voltage. The driving circuit generates the second voltage according to the first voltage. The border area includes electro-phoretic particles of the first color or the second color. A voltage difference between the first voltage and the second voltage drives the electro-phoretic particles of the first color or the second color to be maintained to a predetermined position such that the border area maintains displaying the border of the first color or the second color.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: E Ink Holdings Inc.
    Inventors: Hao-Ting Hsu, Chia-Hao Kuo, Yu-Jui Chang
  • Patent number: 10706793
    Abstract: An electro-phoretic display apparatus including an electro-phoretic display panel and a driving circuit is provided. The electro-phoretic display panel includes a display area and a border area. The driving circuit is coupled to the electro-phoretic display panel. The driving circuit is configured to drive the display area to display an image frame according to a first voltage. The driving circuit drives the border area to maintain displaying a white border or a black border according to a second voltage.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 7, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Hao-Ting Hsu, Chia-Hao Kuo, Yu-Jui Chang
  • Publication number: 20180158419
    Abstract: An electro-phoretic display apparatus including an electro-phoretic display panel and a driving circuit is provided. The electro-phoretic display panel includes a display area and a border area. The driving circuit is coupled to the electro-phoretic display panel. The driving circuit is configured to drive the display area to display an image frame according to a first voltage. The driving circuit drives the border area to maintain displaying a white border or a black border according to a second voltage.
    Type: Application
    Filed: November 30, 2017
    Publication date: June 7, 2018
    Applicant: E Ink Holdings Inc.
    Inventors: Hao-Ting Hsu, Chia-Hao Kuo, Yu-Jui Chang
  • Patent number: 9954098
    Abstract: A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes at least a substrate, an isolated structure, a gate, a source, a drain, a deep well, and a body well. The deep well extends under the isolated structure, and the body well is formed in the deep well between the gate and the isolated structure, wherein the body well has a convex region extending under the isolated structure. The deep well has a drive-in region outside the convex region of the body well, and the drive-in region has a lower doping concentration than remainder of the deep well.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 24, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yu-Jui Chang
  • Patent number: 9735291
    Abstract: A semiconductor device includes a substrate; a well region of a first-conductivity-type, disposed in the substrate; a first impurity region of a first-conductivity-type disposed in the well region; a second impurity region of the second-conductivity-type disposed in the well region, the second-conductivity-type being opposite to the first-conductivity-type; a third impurity region disposed in the well region, a portion of the first impurity region overlapping a first portion of the third impurity region, a portion of the second impurity region overlapping a second portion of the third impurity region, and a third portion of the third impurity region being disposed between the first impurity region and the second impurity region; and a fourth impurity region and a barrier layer disposed in the substrate, the fourth impurity region and the barrier layer enclosing the well region from around and below, respectively.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 15, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Ming Chiou, Yu-Jui Chang, Cheng-Chi Lin
  • Publication number: 20170110597
    Abstract: A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region overlaps a portion of the third impurity region. The plurality of branches of the second impurity region are disposed in the third impurity region, and a portion of the third impurity region is disposed between the first impurity region and the second impurity region.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Yu-Jui CHANG, Cheng-Chi LIN
  • Patent number: 9608129
    Abstract: A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region overlaps a portion of the third impurity region. The plurality of branches of the second impurity region are disposed in the third impurity region, and a portion of the third impurity region is disposed between the first impurity region and the second impurity region.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 28, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Jui Chang, Cheng-Chi Lin
  • Patent number: 9553142
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source region disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the source region along a first direction, and a buried layer having the second conductivity type and disposed under an area between the source region and the drain region.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 24, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Jui Chang, Cheng-Chi Lin
  • Publication number: 20160365410
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source region disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the source region along a first direction, and a buried layer having the second conductivity type and disposed under an area between the source region and the drain region.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Inventors: Yu-Jui CHANG, Cheng-Chi LIN
  • Patent number: 9443754
    Abstract: A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 13, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Jui Chang, Cheng-Chi Lin, Shih-Chin Lien
  • Publication number: 20160043180
    Abstract: A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 11, 2016
    Inventors: Yu-Jui CHANG, Cheng-Chi LIN, Shih-Chin LIEN
  • Patent number: 9082841
    Abstract: A semiconductor device includes a substrate, an insulation layer disposed over the substrate, covering a drift region, and including a first edge and a second edge opposite to the first edge, a gate layer covering the first edge of the insulation layer, and a metal layer including a metal portion connected to the gate layer and overlapping the first edge of the insulation layer. The metal portion includes a first edge located closer to a central portion of the insulation layer than an opposite second edge of the metal portion. A distance from the first edge of the metal portion to the first edge of the insulation layer along a channel length direction is a. A distance from the first edge of the insulation layer to the second edge of the insulation layer is L. A ratio of a/L is equal to or higher than 0.46.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: July 14, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Jui Chang, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Publication number: 20150048452
    Abstract: A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Macronix International Co., Ltd.
    Inventors: Chieh-Chih Chen, Yu-Jui Chang, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 8493306
    Abstract: The present invention discloses a source driver and a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a data bus, a plurality of channels, a multiplexer and a plurality of output pads. The channels are connected to the output pads via the multiplexer. Each channel has a latch unit. Data is transmitted on the data bus and stored in the latch units. The source driver is powered by a first supply voltage from the power supply. The method comprises determining whether the first supply voltage is insufficient, and if yes, performing the following steps. First, set the data transmitted on the data bus to be a predetermined value. Then, keep the latch units turned on, thereby the data is sent out from the latch units. Then, keep the multiplexer turned on for outputting a driving voltage based on the data via the output pads.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 23, 2013
    Assignee: Himax Technologies Limited
    Inventors: Chuan-Che Lee, Tsung-Yu Wu, Yu-Jui Chang
  • Patent number: 8159481
    Abstract: The present invention discloses a display driver and related display. The display driver includes: a plurality of level shifters, respectively receiving input signals for outputting shifted signals; a plurality of switches; and a digital-to-analog converter, having a plurality of input terminals electrically connected to outputs of the level shifters respectively via the switches directly; wherein the switches are turned off while the level shifters are in a transition to convert the input signals into the shifted signals.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: April 17, 2012
    Assignee: Himax Technologies Limited
    Inventor: Yu-Jui Chang
  • Patent number: 7973572
    Abstract: An output buffer including a first input stage circuit, a first output stage circuit, a second output stage circuit, a first switching module, and a second switching module is disclosed. The first output stage circuit is coupled to a first data line. The second output stage circuit is coupled to a second data line. The first switching module is coupled between the first input stage circuit and the first output stage circuit. The second switching module is coupled between the first input stage circuit and the second output stage circuit.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: July 5, 2011
    Assignee: Himax Technologies Limited
    Inventor: Yu-Jui Chang
  • Patent number: 7965114
    Abstract: The present invention discloses a source driver and a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a multiplexer, at least two channels and at least two output pads. The channels are connected to the output pads via the multiplexer. The source driver is powered by a first supply voltage from the power supply. The two output pads are connected via a charge sharing switch. The method comprises the following steps. First, determine whether the first supply voltage is insufficient, and if yes, perform the following steps. Turn off the charge sharing switch. Then, disconnect the channels from the output pads by the multiplexer.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: June 21, 2011
    Assignee: Himax Technologies Limited
    Inventors: Chuan-Che Lee, Tsung-Yu Wu, Yu-Jui Chang