Patents by Inventor Yu-Jui Wu
Yu-Jui Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240128626Abstract: A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.Type: ApplicationFiled: November 25, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Yu-Kuang WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
-
Publication number: 20240120313Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
-
Publication number: 20240089607Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.Type: ApplicationFiled: May 29, 2023Publication date: March 14, 2024Applicant: HTC CorporationInventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
-
Publication number: 20240021547Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
-
Patent number: 11848302Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.Type: GrantFiled: December 13, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
-
Publication number: 20230113265Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
-
Publication number: 20230048883Abstract: A wireless communication device includes a transceiver device and a data processing device. The transceiver device receives a frame from a wireless communication channel. The data processing device receives the frame and determines whether at least one of multiple predetermined frames has been received or is about to be received according to the frame. The data processing device enables a batch-frame indication mechanism when determining that said at least one of the multiple predetermined frames has been received or is about to be received. When the batch-frame indication mechanism is enabled, every time when one of the multiple predetermined frames is received, it is buffered in a reception queue instead of issuing a fetch indication, and when a number of predetermined frames buffered in the reception queue reaches a predetermined batch size, the data processing device issues the fetch indication to a back-end processing device.Type: ApplicationFiled: July 18, 2022Publication date: February 16, 2023Applicant: Realtek Semiconductor Corp.Inventors: Yu-Jui Wu, Ting-Wei Huang, Hsuan-Yen Chung
-
Publication number: 20230020015Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.Type: ApplicationFiled: January 13, 2022Publication date: January 19, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jiun-Yun LI, Nai-Wen HSU, Wei-Chih HOU, Yu-Jui WU, Yen CHUANG, Chia-Yu LIU
-
Patent number: 11545463Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.Type: GrantFiled: August 5, 2021Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
-
Publication number: 20220199555Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
-
Patent number: 11276653Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.Type: GrantFiled: October 17, 2019Date of Patent: March 15, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yuan Chen, Jiun-Yun Li, Rui-Fu Xu, Chiung-Yu Chen, Ting-I Yeh, Yu-Jui Wu, Yao-Chun Chang
-
Publication number: 20210375821Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.Type: ApplicationFiled: August 5, 2021Publication date: December 2, 2021Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
-
Patent number: 11088108Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.Type: GrantFiled: June 27, 2019Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
-
Publication number: 20210118826Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
-
Publication number: 20200411467Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
-
Patent number: 9966427Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.Type: GrantFiled: May 13, 2016Date of Patent: May 8, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-Wei Cheng, Hung-Lin Chen, Jui-Chun Weng, Shiuan-Jeng Lin, Tian Sheng Lin, Yu-Jui Wu, Albion Pan, Bob Sun
-
Patent number: 9884758Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.Type: GrantFiled: June 15, 2016Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-Wei Cheng, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu, Yu-Jui Wu, Ching-Hsiang Hu, Ming-Tsung Chen
-
Publication number: 20170330931Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Inventors: Shyh-Wei Cheng, Hung-Lin Chen, Jui-Chun Weng, Shiuan-Jeng Lin, Tian Sheng Lin, Yu-Jui Wu, Albion Pan, Bob Sun
-
Publication number: 20170203962Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.Type: ApplicationFiled: June 15, 2016Publication date: July 20, 2017Inventors: Shyh-Wei Cheng, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu, Yu-Jui Wu, Ching-Hsiang Hu, Ming-Tsung Chen
-
Patent number: 7752807Abstract: An improved watering device comprises a cap member including a fastening portion provided at the upper side thereof for screwing with a container, and including a hollow tapered insertion element couplingly disposed at the lower side thereof and communicating with the fastening portion for forming a water passageway therein, and the cap member containing an air flowing duct extending in the air venting end of the cap member and having an air admitting end formed at the outer portion thereof for screwing with a rotating knob, wherein the air admitting end of the air flowing duct includes a tapered outer thread portion attached thereon so that as screwing with the rotating knob, an air admitting sacs between the inner and outer thread portions may be formed, thereby the outside air may flow into the air flowing duct, any by using the control member, the outflow amount of fluid may be stably regulated.Type: GrantFiled: July 17, 2007Date of Patent: July 13, 2010Inventor: Yu-Jui Wu