Patents by Inventor Yu-Jui Wu

Yu-Jui Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12284548
    Abstract: A wireless communication device includes a transceiver device and a data processing device. The transceiver device receives a frame from a wireless communication channel. The data processing device receives the frame and determines whether at least one of multiple predetermined frames has been received or is about to be received according to the frame. The data processing device enables a batch-frame indication mechanism when determining that said at least one of the multiple predetermined frames has been received or is about to be received. When the batch-frame indication mechanism is enabled, every time when one of the multiple predetermined frames is received, it is buffered in a reception queue instead of issuing a fetch indication, and when a number of predetermined frames buffered in the reception queue reaches a predetermined batch size, the data processing device issues the fetch indication to a back-end processing device.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 22, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yu-Jui Wu, Ting-Wei Huang, Hsuan-Yen Chung
  • Publication number: 20250089575
    Abstract: A method includes epitaxially growing a Ge1-xSnx channel layer over a substrate. The Ge1-xSnx channel layer is in a metastable state. A Ge1-ySny barrier layer is epitaxially grown over the Ge1-xSnx channel layer to form a two-dimensional hole gas in the Ge1-xSnx channel layer. The Ge1-xSnx channel layer and the Ge1-ySny barrier layer are etched to form a first opening and a second opening in the Ge1-xSnx channel layer and the Ge1-ySny barrier layer. A first source/drain electrode and a second source/drain electrode are deposited in the first opening and the second opening, respectively. A gate electrode is formed over the Ge1-ySny barrier layer.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun LI, Yu-Jui WU, Chia-You LIU, Chia-Tse TAI, Tsung-Ying LI
  • Patent number: 12183709
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20240395735
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Publication number: 20240339547
    Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 10, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun LI, Nai-Wen HSU, Wei-Chih HOU, Yu-Jui WU, Yen CHUANG, Chia-Yu LIU
  • Publication number: 20240332170
    Abstract: Some implementations described herein provide an inductor device formed in a substrate of a semiconductor device including an integrated circuit device. The inductor device may use one or more conduction layers that are included in the substrate. Furthermore, the inductor device may be electrically coupled to the integrated circuit device. By forming the inductor device in the substrate of the semiconductor device, an electrical circuit including the inductor device and the integrated circuit device may be formed within a single semiconductor device.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Chien Hung LIU, Harry-HakLay CHUANG, Kuo-Ching HUANG, Yu-Sheng CHEN, Yi Ching ONG, Yu-Jui WU
  • Patent number: 12051756
    Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: July 30, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun Li, Nai-Wen Hsu, Wei-Chih Hou, Yu-Jui Wu, Yen Chuang, Chia-Yu Liu
  • Publication number: 20240120313
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Publication number: 20240021547
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Patent number: 11848302
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20230113265
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Publication number: 20230048883
    Abstract: A wireless communication device includes a transceiver device and a data processing device. The transceiver device receives a frame from a wireless communication channel. The data processing device receives the frame and determines whether at least one of multiple predetermined frames has been received or is about to be received according to the frame. The data processing device enables a batch-frame indication mechanism when determining that said at least one of the multiple predetermined frames has been received or is about to be received. When the batch-frame indication mechanism is enabled, every time when one of the multiple predetermined frames is received, it is buffered in a reception queue instead of issuing a fetch indication, and when a number of predetermined frames buffered in the reception queue reaches a predetermined batch size, the data processing device issues the fetch indication to a back-end processing device.
    Type: Application
    Filed: July 18, 2022
    Publication date: February 16, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yu-Jui Wu, Ting-Wei Huang, Hsuan-Yen Chung
  • Publication number: 20230020015
    Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
    Type: Application
    Filed: January 13, 2022
    Publication date: January 19, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun LI, Nai-Wen HSU, Wei-Chih HOU, Yu-Jui WU, Yen CHUANG, Chia-Yu LIU
  • Patent number: 11545463
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20220199555
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Patent number: 11276653
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 15, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan Chen, Jiun-Yun Li, Rui-Fu Xu, Chiung-Yu Chen, Ting-I Yeh, Yu-Jui Wu, Yao-Chun Chang
  • Publication number: 20210375821
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Application
    Filed: August 5, 2021
    Publication date: December 2, 2021
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Patent number: 11088108
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20210118826
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Publication number: 20200411467
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU