FLASH MEMORY DEVICE AND METHOD THEREOF
A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
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The present application is a Divisional Application of U.S. application Ser. No. 17/575,054, filed on Jan. 13, 2022, which claims priority to U.S. Provisional Application Ser. No. 63/222,642, filed on Jul. 16, 2021, which is herein incorporated by reference.
BACKGROUNDFlash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed. It is used in a wide variety of commercial and military electronic devices and equipment. To store information, flash memory includes an addressable array of memory cells, typically made from floating gate transistors. Common types of flash memory cells include stacked gate memory cells and split gate memory cells. Split gate memory cells have several advantages over stacked gate memory cells, such as lower power consumption, higher injection efficiency, less susceptibility to short channel effects, and over erase immunity.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A strain relaxed buffer layer 55 is disposed over the semiconductor substrate 50. For example, the strain relaxed buffer layer 55 may include silicon germanium (SiGe), and may also be referred to as a SiGe relaxed buffer layer. In some embodiments, the silicon germanium layer may include composition Si(1-x)Gex where x is a number ranging from 0 to 1, indicating the atomic percentage of germanium. In some embodiments, the silicon germanium layer may include composition of Si0.85Ge0.15. In some other embodiments, the silicon germanium layer may include composition of Si0.7Ge0.3. In some other embodiments, the silicon germanium layer may include composition of Si0.6Ge0.4. In some embodiment, the silicon germanium layer may include composition of Si0.84Ge0.16. In some embodiments, the strain relaxed buffer layer 55 is un-doped. The SiGe relaxed buffer layer (e.g., the strain relaxed buffer layer 55) on a Si substrate (e.g., the semiconductor substrate 50) can have a thin layer of Si (e.g., the semiconductor layer 60) deposited on them, creating tension in the thin Si layer. Tensile Si layer have advantageous properties for the basic device in integrated circuits. For example, placing Si in tension increases the mobility of electrons moving parallel to the surface of the semiconductor substrate 50, thus increasing the frequency of operation of the device and the associated circuit. Second, the band offset between the relaxed SiGe and the tensile Si will confine electrons in the Si layer.
A semiconductor layer 60 is disposed over the strain relaxed buffer layer 55. In some embodiments, the semiconductor layer 60 is made of silicon (Si), and may also be referred to as a silicon layer. As a result of being epitaxially grown on the SiGe strain relaxed buffer layer 55, the strained semiconductor layer 60 has the advantage of tensile longitudinal stress, and will serve as a channel layer in the device. In some embodiments, as the semiconductor layer 60 will be buried between the strain relaxed buffer layer 55 and a semiconductor spacer 65, the semiconductor layer 60 can also be referred to as a buried channel layer. In some embodiments, the semiconductor layer 60 is un-doped.
In some embodiments, the thickness of the semiconductor layer 60 depends on the Ge friction in the strain relaxed buffer layer 55. For example, when the Ge percentage of the strain relaxed buffer layer 55 is 15% (e.g., Si0.85Ge0.15), the thickness of the semiconductor layer 60 is in a range from about 18 nm to about 22 nm, such as 20 nm. When the Ge percentage of the strain relaxed buffer layer 55 is 30% (e.g., Si0.7Ge0.3), the thickness of the semiconductor layer 60 is in a range from about 8 nm to about 12 nm, such as 10 nm. When the Ge percentage of the strain relaxed buffer layer 55 is 40% (e.g., Si0.6Ge0.4), the thickness of the semiconductor layer 60 is in a range from about 4 nm to about 8 nm, such as 6 nm.
A semiconductor spacer 65 is disposed over the semiconductor layer 60. In some embodiments, the semiconductor spacer 65 may include silicon germanium (SiGe), and may also be referred to as a SiGe spacer. In some embodiments, the semiconductor spacer 65 is a strain relaxed layer. In some embodiments, the silicon germanium layer may include composition Si(1-x)Gex where x is a number ranging from 0 to 1, indicating the atomic percentage of germanium. In some embodiments, the germanium concentration of the semiconductor spacer 65 may be lower than the germanium concentration of the strain relaxed buffer layer 55. In some embodiments, the germanium concentration of the semiconductor spacer 65 may be substantially equal to the germanium concentration of the strain relaxed buffer layer 55, such as about 16% (e.g., Si0.84Ge0.16). In some embodiments, the semiconductor spacer 65 is un-doped. In some embodiments, the thickness of the semiconductor spacer 65 is in a range from about 25 nm to bout 100 nm. In some embodiments, the semiconductor spacer 65 is thicker than the semiconductor layer 60. In some embodiments, the Si layer 60 is sandwiched between the SiGe relaxed buffer layer 55 and the SiGe spacer 65. Because the conduction band energy of the Si layer 60 is lower than the conduction band energy of the SiGe relaxed buffer layer 55 and the conduction band energy of the SiGe spacer 65, a quantum well is created in the Si layer 60 where carriers (electrons or holes) can be confined in a two-dimension region. Accordingly, the Si layer 60 can also be referred to as a Si quantum well.
A semiconductor layer 70 is disposed over the semiconductor spacer 65. In some embodiments, the semiconductor layer 70 is made of silicon (Si), and may be referred to as a semiconductor layer 70. In some embodiments, the semiconductor layer 70 may also serve as a channel layer in the device. In some embodiments, because the semiconductor layer 70 is a surface layer of the stack of layers 55, 60, 65, and 70, and thus the semiconductor layer 70 can also be referred to as a surface channel layer. In some embodiments, the semiconductor layer 70 is un-doped. In some embodiments, the semiconductor layer 70 is un-doped. In some embodiments, the thickness of the semiconductor layer 70 is in a range from about 3 nm to about 4 nm. In some embodiments, the semiconductor layer 70 is thinner than the semiconductor layer 60.
A gate structure 80 is disposed over the semiconductor layer 70. The gate structure 80 may include a gate dielectric 82, an adhesion metal 83 over the gate dielectric 82, and a gate electrode 84 over the adhesion metal 83. The gate dielectric 82 includes, for example, an oxide, such as silicon oxide (SiO2), aluminum oxide (Al2O3). In some other embodiments, the gate dielectric 82 may include a high-k dielectric material such as oxides of metals (e.g., oxides of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), and the like, or combinations thereof, or multilayers thereof. The adhesion metal 83 may include Ti, Cr, or other suitable adhesion metals. The gate electrode 84 may include Al, Cu, Ag, Au, W, or other suitable gate electrode materials. In some embodiments, the adhesion metal 83 may be made of Ti, and the gate electrode 84 is made of Au. The thickness of the adhesion metal 83 is in a range from about 5 nm to about 10 nm, and the thickness of the gate electrode 84 is in a range from about 75 nm to about 150 nm.
Source/drain regions 90 are disposed over the substrate 50 and on opposite sides of the gate structure 80. In some embodiments, the source/drain regions 90 may be doped regions extending in the strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70. The dopants of the source/drain regions 90 may be n-type dopants such as phosphorus (P), and the dopant concentration may be in a range from about 1×1019 to about 5×1020. Therefore, the device 10 of
Source/drain contacts 95 are disposed over the source/drain regions 90, respectively. In some embodiments, each of the source/drain contacts 95 may include an adhesion metal 96 and a contact electrode 97 over the adhesion metal 96. The adhesion metal 96 may include Ti, Cr, or other suitable adhesion metals. The contact electrode 97 may include Al, Cu, Ag, Au, W, or other suitable electrode materials. In some embodiments, the adhesion metal 96 may be made of Ti, and the contact electrode 97 is made of Au. The thickness of the adhesion metal 96 is in a range from about 5 nm to about 10 nm, and the thickness of the contact electrode 97 is in a range from about 75 nm to about 150 nm.
In
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Note that the threshold voltage for the device turn-off (e.g., V7) is higher than the threshold voltage for the device turn-on (e.g., V1), which can be attributed to the presence of the semiconductor layer 70 for the backward sweep. For the forward sweep, due to the poor quality of the oxide interface, there is no surface channel formed at the semiconductor layer 70, and thus the buried channel is formed first at the semiconductor layer 60. Thus, the turn-on threshold voltage can be defined as the gate voltage required for the semiconductor layer 60 to be populated with carriers. For the backward sweep, the device is operated at higher gate voltages and both channels are accumulated with carriers. With a decreasing gate voltage, the surface channel (semiconductor layer 70) is depleted first followed by the depletion of the buried channel (semiconductor layer 60). For the surface channel (semiconductor layer 70), the effective capacitance is larger than that for the buried channel (semiconductor layer 60). Furthermore, at high gate voltages, the device has a smaller carrier density than the saturation density in the buried channel (stage III). Thus, a smaller voltage drop is required to deplete the carriers in both channels for the device turn-off. As a result, the device of
Then, a backward sweep operation is applied to the device of
Because almost all electrons trapped by the oxide interface are released, when a forward sweep operation is again applied to the device of
As a result, once a forward sweep operation is applied to the device 10 of
In a program operation, a program voltage VP is applied to the gate structure 80 of the memory device 10. In some embodiments, the program voltage VP is a positive voltage. The positive voltage for the program operation is high enough to trigger the electrons tunnel from the semiconductor layer 60 to the semiconductor layer 70, and then be trapped by the oxide interface of the gate dielectric 82. For example, as discussed in
In an erase operation, an erase voltage VE is applied to the gate structure 80 of the memory device 10. In some embodiments, the program voltage VP is a negative voltage. The voltage for the erase operation is negative enough to de-trap the electrons trapped at the oxide interface of the gate dielectric 82. As discussed in
In some embodiments, the absolute value of the minimum program voltage VP for programming the memory device is lower than the absolute value of the maximum erase voltage VE for erasing the memory device 10. This is because, as mentioned above, a great value of negative voltage is needed to de-trap the electrons from the oxide interface.
As shown in
For instance, during a read operation of an un-programed device 10, because the read voltage Vread is greater than the threshold voltage V11 of the un-programed device 10, the un-programed device 10 will be turn on, thereby increasing the drain current of the un-programed device 10. Accordingly, data ‘1’ can be read out from the un-programed device 10. However, during a read operation of a programed device 10, because the read voltage Vread is lower than the threshold voltage V12 of the programed device 10, and is unable to turn on the programed device 10. Accordingly, drain current of the programed device 10 will not increase, and data ‘0’ can be read out from the programed device 10. That is, if a memory device 10 is un-programed, the drain current may have a logic level of ‘1’; if a memory device 10 is programed, the drain current may have a logic level of ‘0’. It is noted that, as the memory device 10 can be electrically erased and reprogrammed, the memory device 10 can also be referred to as a flash memory device.
Reference is made to
A strain relaxed buffer layer 55, a semiconductor layer 60, a semiconductor spacer 65, and a semiconductor layer 70 are sequentially deposited over the semiconductor substrate 50. In some embodiments, the strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 may be deposited by suitable process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable deposition process. In an example where the strain relaxed buffer layer 55 is made of SiGe, an ultrahigh vacuum chemical vapor deposition (UHVCVD) may be performed with SiH4 and GeH4 as the precursors. A patterned mask M1 is formed over the semiconductor layer 70. In some embodiments, the patterned mask M1 may include openings O1 exposing portions of the semiconductor layer 70 within the first device region 50A of the semiconductor substrate 50, and may include openings O2 exposing other portions of the semiconductor layer 70 within the second device region 50B of the semiconductor substrate 50. In some embodiments, the patterned mask M1 may be formed by photolithography process. The patterned mask M1 may be a photoresist, or may be a hard mask.
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The gate structure 80, the source/drain regions 90, and the underlying semiconductor layers 60 and 70 (channel regions) collectively form a first device 10 within the first device region 50A of the substrate 50. In some embodiments, the first device 10 may be a flash memory device as discussed above with respect to
On the other hand, the gate structures 180, 185, the source/drain regions 190, and the underlying semiconductor layers 60 and 70 (channel regions) collectively form a second device 20 within the second device region 50B of the substrate 50. In some embodiments, the second device region 50B can be referred to as a quantum dot device. This is because, when the gate structures 180 and 185 are applied with certain biases, carriers may be confined within the channel regions (e.g., semiconductor layers 60 and 70) between the gate structures 180 and 185, resulting in a quantum confinement in one-dimension. A gate-defined quantum dot device is then formed.
Reference is made to
In some embodiments, the strain relaxed buffer layer 355 is made of GeSi, the semiconductor layer 360 is made of Ge, the semiconductor spacer 365 is made of GeSi, and the semiconductor layer 370 is made of Ge.
In some other embodiments, the strain relaxed buffer layer 355, the semiconductor layer 360, the semiconductor spacer 365, and the semiconductor layer 370 are made of GeSi. In some embodiments, the semiconductor spacer 365 may include composition Ge(1-y)Siy where y is a number ranging from 0 to 1, indicating the atomic percentage of silicon in the semiconductor spacer 365. On the other hand, the semiconductor layers 360 and 370 may include composition Ge (1-x) Six where x is a number ranging from 0 to 1, indicating the atomic percentage of silicon in the semiconductor layers 360 and 370. In some embodiments, y is greater than x. Stated another way, the atomic percentage of silicon in the semiconductor spacer 365 is higher than the atomic percentages of silicon in the semiconductor layers 360 and 370. In some embodiments, the atomic percentages of silicon in the semiconductor layers 360 and 370 are substantially the same. In some embodiments, the difference between the atomic percentage of silicon in the semiconductor layer 460 and the atomic percentage of silicon in the semiconductor layer 470 is less than 2%.
The deposition of the strain relaxed buffer layer 355, the semiconductor layer 360, the semiconductor spacer 365, and the semiconductor layer 370 may be similar to the deposition of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
Source/drain regions 390 are disposed in the strain relaxed buffer layer 355, the semiconductor layer 360, the semiconductor spacer 365, and the semiconductor layer 370. The source/drain regions 390 may be doped regions, in which the dopants of the source/drain regions 390 may be p-type dopants, such as boron (B). Accordingly, the memory device 32 is a p-type memory device. The formation of the source/drain regions 390 may be similar to the source/drain regions 90, the different is that p-type dopant is used in the implantation process for forming the source/drain regions 390.
In some embodiments, the semiconductor layer 460 is made of gallium arsenide (GaAs), the semiconductor spacer 465 is made of aluminum gallium arsenide (AlGaAs), and the semiconductor layer 470 is made of gallium arsenide (GaAs).
In some other embodiments, the semiconductor layer 460 is made of indium gallium arsenide (InGaAs), the semiconductor spacer 465 is made of indium aluminum arsenide (InAlAs), and the semiconductor layer 470 is made of indium gallium arsenide (InGaAs).
In some other embodiments, the semiconductor layer 460 is made of gallium nitride (GaN), the semiconductor spacer 465 is made of aluminum gallium nitride (AlGaN), and the semiconductor layer 470 is made of gallium nitride (GaN).
The deposition of the semiconductor layer 460, the semiconductor spacer 465, and the semiconductor layer 470 may be similar to the deposition of the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
Source/drain regions 490 are disposed in the semiconductor layer 460, the semiconductor spacer 365, and the semiconductor layer 470. The source/drain regions 490 may be doped regions. In some embodiments, the dopants of the source/drain regions 490 may be p-type dopants, such as boron (B), and the memory device 33 is a p-type memory device. In some other embodiments, the dopants of the source/drain regions 490 may be n-type dopants, such as phosphorus (P), and the memory device 33 is an n-type memory device. The formation of the source/drain regions 490 may be similar to the source/drain regions 90 discussed in
In some embodiments, the strain relaxed buffer layer 555 is made of germanium (Ge), the semiconductor layer 560 is made of germanium tin (GeSn), the semiconductor spacer 365 is made of germanium (Ge), and the semiconductor layer 570 is made of germanium tin (GeSn).
The deposition of the strain relaxed buffer layer 555, the semiconductor layer 560, the semiconductor spacer 565, and the semiconductor layer 570 may be similar to the deposition of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
Source/drain regions 590 are disposed in the strain relaxed buffer layer 555, the semiconductor layer 560, the semiconductor spacer 565, and the semiconductor layer 570. The source/drain regions 590 may be doped regions. In some embodiments, the dopants of the source/drain regions 590 may be p-type dopants, such as boron (B), and the memory device 34 is a p-type memory device. In some other embodiments, the dopants of the source/drain regions 590 may be n-type dopants, such as phosphorus (P), and the memory device 34 is an n-type memory device. The formation of the source/drain regions 590 may be similar to the source/drain regions 90 discussed in
In some embodiments, the channel structure CH1 may include the stack of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
In some embodiments, the fin structure F2 (as well as the channel region CH2) may include the stack of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
In some embodiments, each nanowire NW3 may include the stack of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
In some embodiments, each nanowire NW4 may include the stack of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
In some embodiments, each nanowire NW5 may include the stack of strain relaxed buffer layer 55, the semiconductor layer 60, the semiconductor spacer 65, and the semiconductor layer 70 as discussed in
According to the aforementioned embodiments, it can be seen that the present disclosure offers advantages in fabricating integrated circuits. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that a novel flash memory device is provided using Si/SiGe heterostructure. Furthermore, another advantage is that the novel flash memory device can be integrated with logic device and quantum device on the same material platform, enabling quantum systems on a chip (QSOC) device. This can further enable cost- and performance-effective large-scale quantum computers, and will reduce the wiring complexity, heating, and latency. Another advantage is that the carriers tunneling through the crystal SiGe layer suppressing the oxide breakdown and resulting in high endurance with a single oxide layer deposition required, simplifying the fabrication process. Yet another advantage is that the device can be operated over 10000 times without memory window degradation. The device has retention (over 10000s) with a greater threshold window. The device can further be operated under temperature from about 4K to about 120K (over 10000 times) without memory window degradation.
In some embodiments of the present disclosure, a flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure. In some embodiments, the semiconductor spacer is thicker than the semiconductor quantum well layer and the semiconductor channel layer. In some embodiments, a germanium atomic percentage of the semiconductor spacer is higher than a germanium atomic percentage of the semiconductor quantum well layer and a germanium atomic percentage of the semiconductor channel layer. In some embodiments, the flash memory device further includes a strain relaxed buffer layer between the semiconductor quantum well layer and the substrate. In some embodiments, the strain relaxed buffer layer is formed of the second semiconductor material. In some embodiments, the semiconductor quantum well layer, the semiconductor spacer, and the semiconductor channel layer are un-doped. In some embodiments, in a program operation of the flash memory device, a drain current increases when a gate voltage applied to the gate structure increases from a first level to a second level, the drain current is saturated when the gate voltage applied to the gate structure increases from the second level to a third level, and the drain current decreases when the gate voltage applied to the gate structure increases from the third level to a fourth level. In some embodiments, a voltage for programming the flash memory device is a positive voltage, and a voltage for erasing the flash memory device is a negative voltage. In some embodiments, an absolute value of a minimum voltage for programming the flash memory device is lower than an absolute value of a maximum voltage for erasing the flash memory device.
In some embodiments of the present disclosure, an integrated circuit includes a substrate, a flash memory device over a first region of the substrate, and a gate-defined quantum dot device over a second region of the substrate. The flash memory device includes a first portion of a first semiconductor layer over the substrate; a first portion of a semiconductor spacer over the first semiconductor layer; a first portion of a second semiconductor layer over the semiconductor spacer; first source/drain regions over the substrate; and a first gate structure over the second semiconductor layer and between the first source/drain regions. The gate-defined quantum dot device includes a second portion of the first semiconductor layer over the substrate; a second portion of the semiconductor spacer over the first semiconductor layer; a second portion of the second semiconductor layer over the semiconductor spacer; second source/drain regions over the substrate; and a second gate structure and a third gate structure over the second semiconductor layer, wherein the second gate structure and the third gate structure are between the second source/drain regions. In some embodiments, the integrated circuit further includes a strain relaxed buffer layer between the substrate and the first semiconductor layer. In some embodiments, bottom surfaces of the first source/drain regions are lower than a top surface of the strain relaxed buffer layer and are higher than a bottom surface of the strain relaxed buffer layer. In some embodiments, the second and third gate structures have separated gate metals but a shared gate dielectric. In some embodiments, a germanium atomic percentage of the semiconductor spacer is higher than a germanium atomic percentage of the first semiconductor layer and a germanium atomic percentage of the second semiconductor layer. In some embodiments, the semiconductor spacer is thicker than the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is thicker than the second semiconductor layer.
In some embodiments of the present disclosure, a method includes performing a program operation to write a data in a flash memory device, the flash memory device comprising: a substrate; a semiconductor quantum well layer over the substrate; a semiconductor spacer over the semiconductor quantum well layer; a semiconductor channel layer over the semiconductor spacer; a gate structure over the semiconductor channel layer; and source/drain regions over the substrate and on opposite sides of the gate structure, wherein the program operation is performed such that a threshold voltage of the flash memory device increases from a first level to a second level; and performing an erase operation to erase the data from the flash memory device, wherein the erase operation is performed such that the threshold voltage of the flash memory device decreases from the second level back to the first level. In some embodiments, during the program operation a drain current increases when a gate voltage applied to the gate structure increases from the first voltage to the second voltage, the drain current is saturated when the gate voltage applied to the gate structure increases from the second voltage to a third voltage, and the drain current decreases when the gate voltage applied to the gate structure increases from the third voltage to a fourth voltage. In some embodiments, an absolute value of a minimum voltage for the program operation is lower than an absolute value of a maximum voltage for the erase operation. In some embodiments, a voltage for the program operation is a positive voltage, and a voltage for the erase operation is a negative voltage. In some embodiments, the method further includes performing a read operation to the flash memory device, wherein a gate voltage applied to the gate structure during the read operation is between the first level and the second level.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A flash memory device, comprising:
- a substrate;
- a semiconductor quantum well layer formed of a first semiconductor material and disposed over the substrate;
- a semiconductor spacer formed of a second semiconductor material and disposed over the semiconductor quantum well layer;
- a semiconductor channel layer formed of the first semiconductor material and disposed over the semiconductor spacer;
- a gate structure over the semiconductor channel layer; and
- source/drain regions over the substrate and on opposite sides of the gate structure.
2. The flash memory device of claim 1, wherein the semiconductor spacer is thicker than the semiconductor quantum well layer and the semiconductor channel layer.
3. The flash memory device of claim 1, wherein a germanium atomic percentage of the semiconductor spacer is higher than a germanium atomic percentage of the semiconductor quantum well layer and a germanium atomic percentage of the semiconductor channel layer.
4. The flash memory device of claim 1, further comprising a strain relaxed buffer layer between the semiconductor quantum well layer and the substrate.
5. The flash memory device of claim 4, wherein the strain relaxed buffer layer is formed of the second semiconductor material.
6. The flash memory device of claim 1, wherein the semiconductor quantum well layer, the semiconductor spacer, and the semiconductor channel layer are un-doped.
7. The flash memory device of claim 1, wherein in a program operation of the flash memory device,
- a drain current increases when a gate voltage applied to the gate structure increases from a first level to a second level,
- the drain current is saturated when the gate voltage applied to the gate structure increases from the second level to a third level, and
- the drain current decreases when the gate voltage applied to the gate structure increases from the third level to a fourth level.
8. The flash memory device of claim 1, wherein a voltage for programming the flash memory device is a positive voltage, and a voltage for erasing the flash memory device is a negative voltage.
9. The flash memory device of claim 1, wherein an absolute value of a minimum voltage for programming the flash memory device is lower than an absolute value of a maximum voltage for erasing the flash memory device.
10. An integrated circuit, comprising:
- a substrate;
- a flash memory device over a first region of the substrate, comprising: a first portion of a first semiconductor layer over the substrate; a first portion of a semiconductor spacer over the first semiconductor layer; a first portion of a second semiconductor layer over the semiconductor spacer; first source/drain regions over the substrate; and a first gate structure over the second semiconductor layer and between the first source/drain regions; and
- a gate-defined quantum dot device over a second region of the substrate, comprising: a second portion of the first semiconductor layer over the substrate; a second portion of the semiconductor spacer over the first semiconductor layer; a second portion of the second semiconductor layer over the semiconductor spacer; second source/drain regions over the substrate; and a second gate structure and a third gate structure over the second semiconductor layer, wherein the second gate structure and the third gate structure are between the second source/drain regions.
11. The integrated circuit of claim 10, further comprising:
- a strain relaxed buffer layer between the substrate and the first semiconductor layer.
12. The integrated circuit of claim 11, wherein bottom surfaces of the first source/drain regions are lower than a top surface of the strain relaxed buffer layer and are higher than a bottom surface of the strain relaxed buffer layer.
13. The integrated circuit of claim 10, wherein the second and third gate structures have separated gate metals but a shared gate dielectric.
14. The integrated circuit of claim 10, wherein a germanium atomic percentage of the semiconductor spacer is higher than a germanium atomic percentage of the first semiconductor layer and a germanium atomic percentage of the second semiconductor layer.
15. The integrated circuit of claim 10, wherein the semiconductor spacer is thicker than the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is thicker than the second semiconductor layer.
16. An integrated circuit, comprising:
- a substrate;
- a flash memory device over a first region of the substrate, comprising: a first portion of a first silicon layer over the substrate; a first portion of a silicon germanium spacer over the first silicon layer; a first portion of a second silicon layer over the silicon germanium spacer; first source/drain regions over the substrate; and a first gate structure over the second silicon layer and between the first source/drain regions; and
- a gate-defined quantum dot device over a second region of the substrate, comprising: a second portion of the first silicon layer over the substrate; a second portion of the silicon germanium spacer over the first silicon layer; a second portion of the second silicon layer over the silicon germanium spacer; second source/drain regions over the substrate; and a second gate structure and a third gate structure over second silicon layer,
- wherein the second gate structure and the third gate structure are between the second source/drain regions.
17. The integrated circuit of claim 16, wherein:
- the second gate structure comprises a first gate dielectric layer and a first gate metal,
- the third gate structure comprises a second gate dielectric layer and a second gate metal, and
- the first gate metal is spaced apart from the second gate metal.
18. The integrated circuit of claim 17, wherein the first gate dielectric layer is in contact with the second gate dielectric layer.
19. The integrated circuit of claim 16, wherein the second gate structure and the third gate structure are laterally between the second source/drain regions.
20. The integrated circuit of claim 16, wherein the silicon germanium spacer is thicker than the first silicon layer and the second silicon layer, and the first silicon layer is thicker than the second silicon layer.
Type: Application
Filed: Jun 13, 2024
Publication Date: Oct 10, 2024
Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu), NATIONAL TAIWAN UNIVERSITY (TAIPEI)
Inventors: Jiun-Yun LI (Taipei City), Nai-Wen HSU (Pingtung County), Wei-Chih HOU (Hsinchu City), Yu-Jui WU (Taipei City), Yen CHUANG (Kaohsiung City), Chia-Yu LIU (Taoyuan City)
Application Number: 18/742,191