Patents by Inventor Yu-jung Chang

Yu-jung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11147843
    Abstract: The present invention provides a method of preventing or treating obesity by administering the probiotic bacterium of a novel Parabacteroides goldsteinii strain to the subject in need. The novel Parabacteroides goldsteinii strain is derived from the gastrointestinal tract of an individual and has better aero-tolerance and better acid-tolerance therefore it has better environmental tolerance to adapt to different living environments. The novel Parabacteroides goldsteinii strain not only can effectively prevent the weight gain of the individual, but also can effectively slow down the weight gain of the obese individual; therefore, the novel Parabacteroides goldsteinii strain of the present invention can be used for preparing a pharmaceutical composition for prevention and/or treating obesity.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 19, 2021
    Assignee: MULTISTARS BIOTECHNOLOGY COMPANY LIMITED
    Inventors: Po-I Wu, Chih-Jung Chang, Yu-Ling Tsai, Tzu-Lung Lin
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Patent number: 11138361
    Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Patent number: 11137590
    Abstract: A tunable optical device including a substrate, at least one support unit, a flexible frame, an elastic component, a first reflector, and at least one actuator is provided. The support unit is fixed onto the substrate. The flexible frame is connected to the support unit and suspended above the substrate. The elastic component is connected to the flexible frame. A stiffness of the elastic component in the Z-axis is smaller than a stiffness of the flexible frame in the Z-axis. The Z-axis direction is parallel to a normal direction of the substrate. The first reflector is connected to the elastic component. The actuator is located between the flexible frame and the substrate or located between the first reflector and the substrate.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 5, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Jung Chang, Jing-Yuan Lin, Chun-Kai Mao, Jien-Ming Chen, Yu-Sheng Hsieh
  • Publication number: 20210302690
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: Hsiang-Chin LIN, Shou-Jen LIU, Guan-Bo WANG, Kai-Po FAN, Chan-Jung HSU, Shao-Chung CHANG, Shih-Wei HUNG, Ming-Chun HSIEH, Wei-Pin CHIN, Sheng-Zong CHEN, Yu-Huai LIAO, Sin-Hong LIN, Wei-Jhe SHEN, Tzu-Yu CHANG, Kun-Shih LIN, Che-Hsiang CHIU, Sin-Jhong SONG
  • Publication number: 20210297765
    Abstract: The present disclosure provides an ear tip. The ear tip includes a main body, a first conductive element at least partially embedded in the main body, a second conductive element at least partially embedded in the main body and spaced apart from the first conductive element. The main body includes a central portion having a top and a tail portion extending from the top of the central portion. The first conductive element is proximal to the top of the central portion and the second conductive element is distal from the top of the central portion. A wearable device is also disclosed.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Tau HUANG, Yu-Jung CHANG
  • Patent number: 11119469
    Abstract: A method includes calculating a processing tool offset for a processing tool based on process control parameters, wherein the processing tool offset is a first portion of a process offset time attributable to a processing tool. The method further includes calculating a product offset based on the process control parameters, wherein the product tool offset is a second portion of the process offset time attributable to a product. The method further includes determining whether the product offset is stable based on a difference between a processing time for different products being within a pre-determined tolerance and a number of processed wafers exceeding a threshold amount. The method further includes calculating an offset time for processing the product using the processing tool based on the calculated processing tool offset, without considering the product offset in response to a determination that the product offset is stable.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hsi Nan, Yu-Hsiu Fu, Chia-Jung Chang
  • Patent number: 11121106
    Abstract: In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Chia-Wei Wang, Hui-Jung Tsai, Yu-Tzu Chang
  • Patent number: 11116803
    Abstract: The present disclosure provides a use of Parabacteroides goldsteinii for treating lung cancer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 14, 2021
    Assignee: MULTISTARS BIOTECHNOLOGY COMPANY LIMITED
    Inventors: Po-I Wu, Chih-Jung Chang, Yu-Ling Tsai
  • Publication number: 20210279397
    Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Inventors: Pochun WANG, Yu-Jung CHANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG
  • Publication number: 20210257351
    Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.
    Type: Application
    Filed: June 16, 2020
    Publication date: August 19, 2021
    Inventors: Yung Feng Chang, Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee, Tung-Heng Hsieh, Chun-Chia Hsu
  • Publication number: 20210242212
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Patent number: 11070427
    Abstract: An electronic device for updating firmware in a target device over the air includes a dispatching module and a firmware over the air (FOTA) core. The dispatching module is configured to establish a communication link between the electronic device and the target device. The FOTA core is configured to receive information corresponding to updated firmware via the established communication link.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 20, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jian Feng Lee, Yu-Jung Chang
  • Patent number: 11062075
    Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Patent number: 11062074
    Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Min-Yuan Tsai, Wen-Ju Yang
  • Patent number: 11048849
    Abstract: An integrated circuit includes a first active region, a second active region, a third active region, a first contact and a second contact. The first active region and the second active region are separated from each other in a first direction, and are located on a first level. The third active region is located on the first level and is separated from the second active region in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first contact and the third active region, is electrically coupled to the first contact, and is located on a third level different from the first level and the second level.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Hui-Zhong Zhuang, Yu-Jung Chang
  • Patent number: 11004855
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Publication number: 20210113492
    Abstract: The present disclosure provides a method for inhibiting proliferation and metastasis of cancer cells by using a naphthoquinone derivative.
    Type: Application
    Filed: July 9, 2020
    Publication date: April 22, 2021
    Inventors: Linyi Chen, Yu-Jung Chang, Yen-Chi Tsao, Chun-Hsien Wang
  • Patent number: 10986015
    Abstract: A system and method for ensuring reliable network communication for a multi-node server is disclosed. The multi-node server includes a first node having a port operable to transmit data packets. A first internal switch has a downstream port coupled to the port of the first node, an interconnection port, and uplink ports coupled to the network. The uplink ports routes data packets from the first node to the network. A second internal switch has a downstream port, an interconnection port coupled to the interconnection port of the first internal switch, and an uplink port coupled to the network. On failure of network communication at the uplink ports of the first internal switch, data packets from the first node are routed through the interconnection ports and through the uplink port of the second internal switch to the network.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 20, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Meng-Huan Hsieh, Yu-Jung Chang, Te-Kuai Liu
  • Publication number: 20200364315
    Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.
    Type: Application
    Filed: September 20, 2019
    Publication date: November 19, 2020
    Inventors: Yu-Jung Chang, Min-Yuan Tsai, Wen-Ju Yang