Patents by Inventor Yu Kang

Yu Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10683454
    Abstract: The present invention relates to a phosphor, a method for preparing the phosphor, an optoelectronic component, and a method for producing the optoelectronic component. The phosphor has the following general formula: La3(1?x)Ga1?yGe5(1?z)O16: 3xA3+, yCr3+, 5zB4+, where x, y, and z do not equal to 0 simultaneously; A represents at least one of Gd and Yb; B represents at least one of Sn, Nb, and Ta. For the phosphor, its emission spectrum is within a red visible light region and a near-infrared region when excited by blue visible light, purple visible light or ultraviolet light; and it has a wide reflection spectrum and a high radiant flux. Therefore, it can be used in optoelectronic components such as LEDs to meet requirements of current medical testing, food composition analysis, security cameras, iris/facial recognition, virtual reality, gaming notebook and light detection and ranging applications.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Veeramani Rajendran, Mu-Huai Fang, Ru-Shi Liu, Ho Chang, Kuang-Mao Lu, Yan-Shen Lin, Chieh-Yu Kang, Gabriel Nicolo A. De Guzman, Shu-Fen Hu
  • Patent number: 10684657
    Abstract: A multi-axis hinge includes a first shaft, a first rotary member pivotally connected to the first shaft, a second shaft fixed to the first rotary member, a second rotary member pivotally connected to the second shaft, a first switching pin movably configured at the first rotary member, and a switching member fixed to the first shaft. The switching member includes a switching recess. When the first switching pin is located at the switching recess of the switching member, the second rotary member is rotatable relatively to the first rotary member. The second rotary member includes a switching recess. When the first switching pin is located at the switching recess of the second rotary member, the second rotary member is fixed to the first rotary member. An electronic device with the multi-axis hinge is also disclosed therein.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 16, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yu-Kang Lin, Yu-Min Liu, Yen-Chung Chen
  • Publication number: 20200186171
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Chih-Kang Yeh
  • Patent number: 10680145
    Abstract: The present disclosure provides an LED package structure and a method for manufacturing the LED package structure. The LED package structure includes: a chip scale package (CSP) light emitting element and a shading layer, where the CSP light emitting element includes a light emitting chip, and the light emitting chip includes an electrode group located on a bottom surface of the light emitting chip, the shading layer is disposed on a bottom surface and/or a side surface of the CSP light emitting element. An LED package structure according to the present disclosure solves a problem that the blue light leaking from the bottom surface of the LED chip interferes with the emission color of the CSP emitting device, and reduces the luminous efficiency of the emitting device.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 9, 2020
    Assignee: EVERLIGHT ELECTRONICS CO., LTD.
    Inventors: Ke-Hao Pan, Sheng-Wei Chou, Yi-Sheng Lan, Chia-Fong Chou, Chung-Chuan Hsieh, Jen-Hao Pan, Hao-Yu Yang, Chieh-Yu Kang, Tzu-Lun Tseng
  • Patent number: 10662588
    Abstract: A friction apparatus is provided. The friction apparatus includes: a first member having a first surface; and a second member having a second surface that contacts the first surface, and moving while in contact with the first member, wherein at least one of the first surface and the second surface is hardened.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: May 26, 2020
    Assignee: KOREA RAILROAD RESEARCH INSTITUTE
    Inventors: Yong Hyeon Cho, Jin Yu Choi, Yun Suk Kang, Joo Uk Kim
  • Patent number: 10664639
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 10665556
    Abstract: A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Wu, Yu-Wei Shang, Chung-Ruei Kang
  • Patent number: 10657303
    Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 19, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, Ching-Ho Lin
  • Patent number: 10651986
    Abstract: A method for controlling an antenna array is provided, which includes following steps. Associations with a plurality of mobile devices are established, and at least one characteristic parameter table corresponding to the mobile devices is generated. When a plurality of transmission request signals are received simultaneously and the mobile devices are divided into a user group, a multi-user antenna index of the antenna array is generated based on the at least one characteristic parameter table, and a plurality of data streams corresponding to the mobile devices are transmitted simultaneously through the antenna array. When the transmission request signals are received simultaneously and the mobile devices are not divided into the user group, a single-user antenna index of the antenna array is generated based on the at least one characteristic parameter table, and the data streams corresponding to the mobile devices are transmitted one-by-one through the antenna array.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 12, 2020
    Assignee: Wistron NeWeb Corp.
    Inventors: Nai-Yu Tseng, Fu-Ming Kang, Chieh-Wen Cheng, Chun-Hsiung Chuang, Ho-ren Chen
  • Publication number: 20200139343
    Abstract: A metal organic framework and a method for preparing the same, and an adsorption device employing the metal organic framework are provided. The metal organic framework includes a 3,5-pyridinedicarboxylic acid and a metal ion, which is an aluminum ion, a chromium ion, or a zirconium ion, wherein the 3,5-pyridinedicarboxylic acid is coordinated to the metal ion.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 7, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Chih LEE, Chang-Yi SHEN, Jiun-Jen CHEN, Yuhao KANG, Shih-Yun YEN, Yu-Xuan WANG
  • Patent number: 10642118
    Abstract: A display substrate is provided. The display substrate includes a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer. In particular, the first insulating layer has a first opening and the second insulating layer has a second opening, wherein the first opening and the second opening are partially overlapped. Further, in a cross-sectional view, the first insulating layer corresponding to the first opening has two first bottom ends, and the second insulating layer corresponding to the second opening has two second bottom ends, a location of a first vertical central line between the two first bottom ends is different from a location of a second vertical central line between the two second bottom ends, and the first vertical central line and the second vertical central line are substantially parallel to a normal direction of the surface.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 5, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Hung-Kun Chen, Yi-Chin Lee, Hong-Kang Chang, Yu-Chien Kao, Jui-Ching Chu, Li-Wei Sung, Hui-Min Huang
  • Patent number: 10641331
    Abstract: A ball cage for ball bearing includes a first race, a second race, a plurality of first ribs equiangularly arranged on the first race with a first curved groove defined between each two adjacent first ribs, and a plurality of second ribs equiangularly arranged on the second race with a second curved groove defined between each two adjacent second ribs. The first ribs are respectively and partially stacked on the second ribs so that each first curved groove is combined with one respective second curved groove to create a respective ball accommodation chamber. Thus, the ball cage can be commonly used for ball bearings lubricated with grease or oil gas to increase the convenience of use.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: May 5, 2020
    Assignee: HIWIN TECHNOLOGIES CORP.
    Inventors: Che-Kang Chang, Yu-Lin Lai, Cheng-Lung Wang
  • Publication number: 20200136025
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.
    Type: Application
    Filed: December 27, 2019
    Publication date: April 30, 2020
    Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
  • Patent number: 10627728
    Abstract: A method for creating a vacuum in a load lock chamber is provided. The method includes building an air-tight environment in the load lock chamber. The method further includes reducing the pressure in a gas tank to a predetermined vacuum pressure. The method also includes enabling an exchange of gas between the load lock chamber and the gas tank when the pressure in the gas tank is at the predetermined vacuum pressure so as to reduce the pressure in the load lock chamber to an adjusted vacuum pressure.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Jung Chang, Yu-Fu Lin, Sheng-Kang Yu
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20200116860
    Abstract: A proximity sensing device which is disposed under the OLED panel and has an emitting module and a receiving module, is provided. The emitting module can emit an invisible light which has a peak wavelength not less than 1000 nm. The receiving module is disposed adjacent to the emitting module and can receive a reflecting light from the reflected invisible light. Therefore, the invisible light passing through the OLED panel will not cause a bright spot on the panel.
    Type: Application
    Filed: March 25, 2019
    Publication date: April 16, 2020
    Applicant: Everlight Electronics Co., Ltd.
    Inventors: Shih-Wen Lai, Yi-Ting Huang, Jing-Hong Lai, Chih-Hao Hsu, Chia-Wei Yang, Chih-Min Lin, Chieh-Yu Kang, Kuang-Mao Lu, Jian-Hong Fan
  • Patent number: 10620163
    Abstract: A method for detecting a defect of a metal plate includes selecting N controllable emitting electromagnetic acoustic transducers EMATs as excitation transducers, and selecting M omnidirectionally receiving EMATs as receiving transducers, exciting an ultrasonic guided wave in a metal plate by a nth controllable emitting EMAT with a predetermined emission angle; determining whether each of M1 omnidirectionally receiving EMATs and the nth controllable emitting EMAT form a scattering group; for the scattering group, solving a position of a scattering point and a direction of a scattering side according to a distance between Tn and Rml, the emission angle and a travel time of the ultrasonic guided wave; performing a curve fitting on all the scattering points in directions of respective scattering sides to obtain a contour image of the defect.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 14, 2020
    Assignees: HUBEI UNIVERSITY OF TECHNOLOGY, TSINGHUA UNIVERSITY, CHINA SPECIAL EQUIPMENT INSPECTION AND RESEARCH INSTITUTE, EDDYSUN (XIAMEN) ELECTRONIC CO., LTD., HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Songling Huang, Xiaochun Song, Gongtian Shen, Wei Zhao, Junming Lin, Yihua Kang, Yu Zhang, Shen Wang
  • Publication number: 20200108592
    Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
  • Publication number: 20200105722
    Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
  • Patent number: 10599410
    Abstract: An electronic device includes a communication circuit that communicates with an external device, a memory configured to store first setting data corresponding to a first time period, and a processor operatively connected with the communication circuit and the memory. The processor receives second setting data corresponding to a second time period from the external device through the communication circuit if a specified time point is reached, deletes at least a portion of the first setting data based on whether a status of a user is a login status or a logout status, and applies the second setting data to the electronic device.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Sik Kim, In Ku Kang, Yu Seung Kim, Tae Hyun Kim, Dong Ho Jang, Eun Jung Hyun