Abstract: Semiconductor structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin rising from the substrate, an isolation feature disposed over the substrate and between the first base fin and the second base fin, a first bottom epitaxial feature over the first base fin, a second bottom epitaxial feature over the second base fin, an isolation layer on the first bottom epitaxial feature, a first source/drain feature over the isolation layer, a second source/drain feature disposed over and in contact with the second bottom epitaxial feature, a contact etch stop layer (CESL) over the first source/drain feature and the isolation feature, a first interlayer dielectric (ILD) layer over the CESL, and a second ILD layer over and in direct contact with the second source/drain feature.

Abstract: A battery cell includes an enclosure and a battery cell stack including C cathode electrodes each comprising a cathode active material layer arranged on a cathode current collector, S separators, and A anode electrodes each comprising an anode active material layer arranged on an anode current collector, wherein A, C, and S are integers greater than one. The anode active material layer includes an anode active material selected from a group consisting of silicon, silicon oxide, silicon alloy, and tin, a solid-state electrolyte comprising an oxysulfide, a conductive additive, and a binder. An electrolyte includes a solvate ionic liquid.

Abstract: An inspection system and an inspection method of a bare circuit board are provided. The inspection system is used for inspecting a bare circuit board. The bare circuit board includes a chip pad and an antenna. The inspection system includes an adapter board, a test device and a measure device. The adapter board includes a chip and a contact structure. The chip is electrically connected to the contact structure. The contact structure touches the chip pad so that the chip is electrically connected to the chip pad. The test device includes a transceiver antenna. The test device and the bare circuit board separate. The measure device is electrically connected to the chip or the transceiver antenna.

Abstract: An electrochemical cell including an electrode including a sulfuric conversion electroactive material, and a solid state electrolyte comprising an oxysulfide; a liquid electrolyte; a separator; and a negative electrode.

Abstract: A time synchronization method used for a time synchronization device is provided. The time synchronization device runs a plurality of Precision Time Protocol (PTP) instances to connect to a plurality of time synchronization domains through a plurality of ports. The time synchronization method includes selecting a grandmaster (GM) clock from the plurality of time synchronization domains; updating clock information of the grandmaster clock; determining whether each of the plurality of ports is a time receiving port or a time transmitting port according to the grandmaster clock; modifying clock attributes of each of the plurality of PTP instances according to whether the corresponding port is the time receiving port or the time transmitting port; and synchronizing, by the plurality of PTP instances, timings of the plurality of time synchronization domains according to the grandmaster clock.

Abstract: A time synchronization method is provided for a time synchronization device, wherein the time synchronization device runs a plurality of precision time protocol (PTP) instances to connect to a plurality of time synchronization domains respectively. The time synchronization method includes determining whether a frequency of a local PTP clock of the time synchronization device is changed; and updating a frequency of a local clock of the time synchronization device with the frequency of the local PTP clock in response to the frequency of the local PTP clock being changed.

Abstract: There is provided an optical engine for a navigation device including a first light source, a second light source, a lens, a barrier structure and an image sensor. The barrier structure has a first space for containing the first light source, a second space for containing the lens and a third space for containing the second light source and the image sensor. The reflected light associated with the first light source propagates to the image sensor via the lens in the second space. The reflected light associated with the second light source propagates to the image sensor via the third space without passing through the lens in the second space.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Abstract: Disclosed is a water flow switching device for sprinkler applications, the features of which include a projecting swing arm having a driven end, an oscillating end, and a supporting flange. The driven end extends to the exterior of an end wall and corresponding to a spray angle control mechanism to form a driven relationship. The oscillating end being located in a gear chamber. The supporting flange is mounted on a pivot seat. The oscillating end includes a first and a second oscillating position. A water shut-off device is disposed in the gear chamber. One side of the device has a first flap end, a second flap end, and a snap-over portion.

Abstract: A display panel, including: a base plate; a plurality of first electrodes being distributed in an array on a side of the base plate and having first edge areas; an isolation structure, provided on a side of the base plate, located on a same side of the base plate as the first electrodes, enclosing a plurality of isolation openings and insulated from the first electrodes, at least part of which are exposed from the isolation openings, the isolation structure includes isolation walls with first surfaces away from the base plate and second surfaces facing the base plate, as well as first side surfaces connecting the first surfaces and the second side surfaces, and at least part of orthographic projections of the first edge areas on the base plate are staggered with orthographic projections of the first side surface on the base plate.

Abstract: A display panel, a display apparatus, and a method for manufacturing a display panel. The display panel includes a substrate, an isolation structure, a light-emitting functional layer, and a first encapsulation layer, and the isolation structure is provided on a side of the substrate, and encloses and forms an opening structure. The light-emitting functional layer is provided on a side of the substrate and includes a plurality of light-emitting units provided within opening structures. The first encapsulation layer is provided on a side of the light-emitting functional layer away from the substrate and includes a plurality of encapsulation portions corresponding to the light-emitting units. Thicknesses of the encapsulation portions corresponding to at least a part of the light-emitting units having different light-emitting colors are different. In the embodiments of the present application, usage reliability of the display panel may be improved.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A display panel, a method for manufacturing a display panel, and a display apparatus. The display panel includes a display region, a non-display region at least partially surrounding the display region, and further includes a base plate, a wiring layer, a light-emitting layer, and an isolation structure. The wiring layer is located on a side of the base plate and includes a metal layer located in the display region and a signal line layer located in the non-display region. The light-emitting layer is located on a side of the wiring layer away from the base plate and includes a plurality of light-emitting units. The isolation structure is located on a side of the wiring layer away from the base plate and is provided with an isolation opening configured to accommodate the light-emitting unit.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: A folding dividing screen structure has at least two screen panels, a plurality of sealing covers, at least one connecting member with a respective vertical through channel on opposite sides of the connecting member, and at least two vertical strips. Each screen panel is secured in an outer frame, the connecting member pivotally connected with the two screen panels via the two vertical strips.