Patents by Inventor Yu Lee

Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Inhibitors of positive strand RNA viruses
    Patent number: 11957667
    Abstract: Methods of treating a disease caused by a positive strand RNA virus. The methods include administering to a subject in need thereof an effective amount of a compound of Formula I or Formula II.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 16, 2024
    Assignee: National Health Research Institutes
    Inventors: Shiow-Ju Lee, Cheng-Wei Yang, Yue-Zhi Lee, Hsing-Yu Hsu
  • Pixel and display device
    Patent number: 11961463
    Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin-Wook Yang, Yu-Chol Kim, Donggyu Lee, Jaekeun Lim, Jae-Hyeon Jeon
  • Automated inspection tool
    Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Controlling threshold voltages through blocking layers
    Patent number: 11961732
    Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Lee, Chung-Chiang Wu, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee
  • INTEGRATED MOTOR AND DRIVE ASSEMBLY
    Publication number: 20240120812
    Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 11, 2024
    Inventors: Chi-Hsiang Kuo, Yi-Yu Lee, Zuo-Ying Wei, Yuan-Kai Liao, Wen-Cheng Hsieh
  • METHOD AND APPARATUS FOR MONITORING AND MANAGING PERFORMANCE OF ARTIFICIAL NEURAL NETWORK MODEL FOR AIR INTERFACE
    Publication number: 20240121633
    Abstract: A method of monitoring and managing performance of an artificial neural network model for an air interface may comprise: receiving, by a network (NW) including a communication node performing a function of monitoring and managing performance of an artificial neural network model, a performance metric of the artificial neural network model from a user equipment (UE); and controlling, by the communication node, activation or deactivation of the artificial neural network model according to the performance metric, wherein the artificial neural network model is activated to improve a main performance metric of a mobile communication system including the communication node and the UE connected through an air interface.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 11, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Han Jun PARK, Yong Jin KWON, An Seok LEE, Heesoo LEE, Yun Joo KIM, Hyun Seo PARK, Jung Bo SON, Yu Ro LEE
  • FLOOR CLEANER
    Publication number: 20240115097
    Abstract: A method of operating a cleaning system is provided herein. The method includes receiving a first battery pack including a first battery controller, receiving a first signal from the first battery controller, outputting, in response to receiving the first signal, a first control signal, operating a motor at a first predetermined constant power based on the first control signal, receiving a second battery pack including a second battery controller, receiving a second signal from the second battery controller, outputting, in response to receiving the second signal, a second control signal, and operating the motor at a second predetermined constant power based on the second control signal.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 11, 2024
    Inventors: Hei Man LEE, Jie YU, Li Feng WANG
  • HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHOD
    Publication number: 20240121995
    Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Jungmin LEE, Chung-chia CHEN, Ji Young CHOUNG, Yu-hsin LIN
  • STACKED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20240120325
    Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: April 11, 2024
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
  • Automated manufacturing of shoe parts with a pickup tool
    Patent number: 11953877
    Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: April 9, 2024
    Assignee: NILE, Inc.
    Inventors: Dragan Jurkovic, Patrick Conall Regan, Chih-Chi Chang, Chang-chu Liao, Ming-Feng Jean, Kuo-Hung Lee, Yen-Hsi Liu, Hung-Yu Wu
  • Method for gating in tomographic imaging system
    Patent number: 11954768
    Abstract: A method for gating in tomographic imaging system includes steps of: (a) performing a tomographic imaging on an object with a target moving periodically along a first axis for acquiring projection images; (b) obtaining projected curves by summing up pixel values along a direction of a second axis perpendicular to the first axis in each projection image; (c) determining a target zone on the projection images, wherein a central position on the first axis of the target zone is corresponding to a position having the largest variation in the projected curves on the first axis; (d) calculating parameter values of pixel values in the target zones and obtaining a curve of a moving cycle of the target according to the parameter values; and (e) selecting the projection images under the same state in the moving cycle for image reconstruction according to the curve of the moving cycle of the target.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: April 9, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sih-Yu Chen, Jhih-Shian Lee, Ya-Chen Chen
  • Sense amplifier circuit with temperature compensation
    Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • OLED light field architectures
    Patent number: 11956994
    Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
  • Wireless communication technology, apparatuses, and methods
    Patent number: 11955732
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Equal divider
    Patent number: 11951766
    Abstract: Disclosed is an equal divider, including a mainframe and a plurality of indicator plates, wherein the mainframe is mainly made up of a plurality of first connecting rods and a plurality of second connecting rods pivoted by a plurality of pivoting structures to form a scissor structure. The mainframe is formed with a plurality of first pivoting parts and a plurality of second pivoting parts. The first pivoting parts and the second pivoting parts pivot the first connecting rods and the second connecting rods. The indicator plate is configured between the first connecting rod and the second connecting rod. The indicator plate is configured with a protruding indicating part. Each indicator plate is configured with a long through groove. The second pivoting part goes through the through groove. The indicating parts and the first pivoting parts maintain a fixed distance along the second axial direction.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: April 9, 2024
    Inventor: Tai-Yu Lee
  • Cold plate
    Patent number: 11956919
    Abstract: A cold plate is provided and includes: a housing disposed with a chamber; a base combined with the housing to form a working space separated from the chamber but connected with the chamber through an interconnecting structure to allow a working medium to flow within the chamber and the working space; a heat transfer structure disposed on the inner side of the base; and a pump disposed within the working space to drive the working medium in the working space. As such, the cold plate can provide better heat dissipation performance.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 9, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-An Chen, Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Wei-Shen Lee
  • Low-K Gate Spacer and Methods for Forming the Same
    Publication number: 20240113202
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Semiconductor Device and Method
    Publication number: 20240112905
    Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Inventors: Ching-Yu Chang, Jei Ming Chen, Tze-Liang Lee
  • PIXEL, DISPLAY DEVICE INCLUDING PIXEL, AND PIXEL DRIVING METHOD
    Publication number: 20240112622
    Abstract: A pixel includes: a light-emitting element including an anode and a cathode, a first transistor including a first and a second electrode and a gate electrode connected with a first node, a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected with a first scan line, a sixth transistor connected between the second electrode of the first transistor and the anode and including a gate electrode connected with a first emission line, and a seventh transistor connected between the anode and an initialization voltage line and including a gate electrode connected with a second scan line. During an initialization period, the third, sixth, and seventh transistors are turned on such that an initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor.
    Type: Application
    Filed: July 20, 2023
    Publication date: April 4, 2024
    Inventors: JIN-WOOK YANG, YU-CHOL KIM, DONGGYU LEE, JAE-HYEON JEON
  • ELECTRONIC DEVICE AND ANTENNA MODULE
    Publication number: 20240113414
    Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.
    Type: Application
    Filed: September 24, 2023
    Publication date: April 4, 2024
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Heng Lin, Li-Chun Lee, Shih-Chia Liu, Jui-Hung Lai, Hung-Yu Yeh