Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

Abstract: A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.

Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

Abstract: A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.

Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

Abstract: A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

Abstract: A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.

Abstract: A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

Abstract: A charge pump circuit includes first and second capacitors, first and second controllable current generating circuits, and an interconnection circuit. A first terminal of the first controllable current generating circuit is coupled to a first plate of the first capacitor. A first terminal of the second controllable current generating circuit is coupled to a first plate of the second capacitor. During a first operation mode, the first controllable current generating circuit refers to a first control input for selectively providing a first current, and the second controllable current generating circuit refers to a second control input for selectively providing a second current. During a second operation mode, the interconnection circuit couples the first plate of the second capacitor to a first power rail, and couples both of the second plate of the second capacitor and the first plate of the first capacitor to an output terminal.

Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.

Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.

Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.