Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

Abstract: A charge pump circuit includes first and second capacitors, first and second controllable current generating circuits, and an interconnection circuit. A first terminal of the first controllable current generating circuit is coupled to a first plate of the first capacitor. A first terminal of the second controllable current generating circuit is coupled to a first plate of the second capacitor. During a first operation mode, the first controllable current generating circuit refers to a first control input for selectively providing a first current, and the second controllable current generating circuit refers to a second control input for selectively providing a second current. During a second operation mode, the interconnection circuit couples the first plate of the second capacitor to a first power rail, and couples both of the second plate of the second capacitor and the first plate of the first capacitor to an output terminal.

Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.

Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.

Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.

Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.

Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.

Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.

Abstract: A compensation apparatus including a primary circuit and a compensation circuit is provided. The primary circuit provides a first voltage, a second voltage, and a first current flowing through a first inductor. The primary circuit includes the first inductor and a function circuit generating an input signal. The first inductor is coupled between a first terminal with the first voltage and a second terminal with the second voltage. The compensation circuit includes a second inductor and a current source circuit. The second inductor is coupled between a third terminal with a third voltage and a fourth terminal with a fourth voltage. The current source circuit outputs a second current flowing through the second inductor. The current source circuit adjusts a frequency of the input signal. The primary circuit and the compensation circuit are coupled via the first inductor and the second inductor.

Abstract: A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.

Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.

Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.

Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.

Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.

Abstract: A frequency synthesizing module includes an operating circuit, for generating a control voltage according to a reference signal and a feedback signal; a controllable oscillating circuit, configured for generating an oscillating signal according to the control voltage and a first control signal, comprising a first oscillating circuit with a first frequency gain, and a second oscillating circuit with a second frequency gain; a feedback circuit, for generating the feedback signal according to the oscillating signal and a second control signal; a control circuit, for generating the first control signal and the second control signal; wherein the control circuit adjusts the first control signal by a first value and adjusts the second control signal by a second value to estimate the first frequency gain of the first oscillating circuit; wherein the first value is proportional to the second value.

Abstract: A frequency synthesizing module includes an operating circuit, for generating a control voltage according to a reference signal and a feedback signal; a controllable oscillating circuit, configured for generating an oscillating signal according to the control voltage and a first control signal, comprising a first oscillating circuit with a first frequency gain, and a second oscillating circuit with a second frequency gain; a feedback circuit, for generating the feedback signal according to the oscillating signal and a second control signal; a control circuit, for generating the first control signal and the second control signal; wherein the control circuit adjusts the first control signal by a first value and adjusts the second control signal by a second value to estimate the first frequency gain of the first oscillating circuit; wherein the first value is proportional to the second value.

Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.

Abstract: A phase detector including a first latch and a control logic is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.

Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.