Abstract: An artificial bone plate unit and an assembleable artificial bone plate are provided. The artificial bone plate unit includes a plate body, multiple connecting pins, connecting holes, drug cavities, and drug-releasing openings. The plate body has two main surfaces and a peripheral surface connected between the two main surfaces. The connecting pins and the connecting holes are formed on the plate body and arranged along the peripheral surface on the plate body. The connecting holes correspond in shape to the connecting pins. The drug cavities are formed in the artificial bone plate unit and are connected to the drug-releasing openings. The artificial bone plate units are connected using the connecting pins and the connecting holes to form the assembleable artificial bone plate. The assembleable artificial bone plate can be bent into the shape of a defect area of the skull, which saves material and time.

Abstract: A quantum dot composite structure and a method for forming the same are provided. The quantum dot composite structure includes: a glass particle including a glass matrix and a plurality of quantum dots located in the glass matrix, wherein at least one of the plurality of quantum dots includes an exposed surface in the glass matrix; and an inorganic protective layer disposed on the glass particle and covering the exposed surface.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A device includes an integrated circuit die attached to a substrate; a lid attached to the integrated circuit die; a sealant on the lid; a spacer structure attached to the substrate adjacent the integrated circuit die; and a cooling cover attached to the spacer structure, wherein the cooling cover extends over the lid, wherein the cooling cover attached to the lid by the sealant. In an embodiment, the device includes a ring structure on the substrate, wherein the ring structure is between the spacer structure and the integrated circuit die.

Abstract: The physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. During a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. The physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. Additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.

Abstract: A method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.

Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.

Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.

Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

Abstract: At least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. The moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. End surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. The vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.

Abstract: In some embodiments, a system for pre-wetting a filter includes a filter, a piping system, a first gas, a second gas, a first buffer tank, and a second buffer tank. The first gas drives the solvent to clean the filter. The two buffer tanks store the solvent discharged from the filter. The second gas selectively drives the solvent in the first buffer tank to return to the filter and then to be discharged into the second buffer tank. Alternatively, the second gas selectively drives the solvent in the second buffer tank to return to the filter and then to be discharged into the first buffer tank.

Abstract: The present invention relates to use of interleukin-22 (IL-22) for treating fatty liver disease by decreasing the levels of transaminases. The use of IL-22 in decreasing the levels of transaminases is also provided.

Abstract: A lead frame for an LED package includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes separated first and second connecting surfaces. Top surfaces of the bonding electrode, the first connecting electrode, and the second connecting electrode are exposed, and support and electrically connect with light emitting chips. LED packages can be mounted on the lead frame and electrically connect with each other. The conductive layout of the lead frame further permits installation of a zener diode which can be connected to the LED packages in series or in parallel.

Abstract: The present invention relates to use of interleukin-22 (IL-22) for treating fatty liver disease by decreasing the levels of transaminases. The use of IL-22 in decreasing the levels of transaminases is also provided.

Abstract: A lead frame for an LED package includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes separated first and second connecting surfaces. Top surfaces of the bonding electrode, the first connecting electrode, and the second connecting electrode are exposed, and support and electrically connect with light emitting chips. LED packages can be mounted on the lead frame and electrically connect with each other. The conductive layout of the lead frame further permits installation of a zener diode which can be connected to the LED packages in series or in parallel.

Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.

Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.

Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.

Abstract: A light emitting diode package (LED) includes two electrodes spaced from each other, an insulating layer sandwiched between the two electrodes, an LED die arranged on the two electrodes and electrically connecting therewith, and an encapsulation layer covering the LED die. Each electrode includes a conductive sheet and a plurality of connecting pins connecting to the conductive sheet. A thickness of the connecting pin is smaller than that of the conductive sheet. A top surface of the connecting pin is coplanar with that of the conductive sheet. The LED package further includes a coating layer coating the connecting pin, part of the coating pin is sandwiched between the top surface of the connecting pin and the encapsulation layer.

Abstract: A light emitting diode package (LED) includes two electrodes spaced from each other, an insulating layer sandwiched between the two electrodes, an LED die arranged on the two electrodes and electrically connecting therewith, and an encapsulation layer covering the LED die and the coating layer. Each electrode includes a conductive sheet and a plurality of connecting pins connecting to the conductive sheet. A thickness of each of the connecting pins is smaller than that of the conductive sheet. A top surface of each of the connecting pins is lower than that of the conductive sheet. The LED package further includes a coating layer coating the connecting pin, part of the coating pin is sandwiched between the top surface of the connecting pin and the encapsulation layer.