Abstract: A method includes forming bottom conductive lines extending along a first direction; forming a first memory cell over one of the bottom conductive lines and a second memory cell over another one of the bottom conductive lines; forming a third memory cell over the one of the bottom conductive lines and a fourth memory cell over the another one of the bottom conductive lines, wherein the third memory cell and the fourth memory cell are at a higher level than the first memory cell and the second memory cell; and forming top conductive lines above the bottom conductive lines, wherein one of the top conductive line vertically overlaps the first and third memory cells, and another one of the top conductive line vertically overlaps the second and fourth memory cells.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A three-dimensional (3D) memory device comprising word lines, bit lines, a 3D memory array, encoding circuits and sensing circuits is provided in the present disclosure. The 3D memory array comprises two-dimensional (2D) memory arrays and stores first to fourth neural network data related to at least one neural network model. Each of the 2D memory arrays is coupled to the word lines and the bit lines, and is configured to receive first and second input voltages and output corresponding first and second output currents. The encoding circuits are respectively coupled to the 2D memory arrays and configured to generate the first and second input voltages respectively based on the first and second neural network data. The sensing circuits are respectively coupled to the 2D memory arrays and configured to generate the third and fourth neural network data respectively based on the first and second output currents.

Abstract: A method for analyzing aortic CT images includes: receiving multiple original CT images and selecting a sequence of chest CT images therefrom; generating, using a part detection model, for each of the chest CT images, a detection result that indicates whether the chest CT image represents an ascending aorta; generating, using a status analysis model, for each of the chest CT images, an analysis result that indicates whether the chest CT image shows aortic dissection; and when determining that at least N chest CT image(s) from consecutive M number of the chest CT images show aortic dissection, determining whether the detection result of at least one of the at least N chest CT image(s) represents an ascending aorta, and if affirmative, generating a type A aortic dissection result or otherwise, generating a type B aortic dissection result.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Abstract: A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub-arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

Abstract: A power supply system with power factor correction (PFC) comprises an AC rectifier, a power factor correction (PFC) conversion circuit, a DC-DC converter, a protocol power delivery (PD) interface and a controller. The AC rectifier is used to rectify the AC input power to generate rectified power. The PFC conversion circuit is used to perform PFC conversion on the rectified power to generate converted power. The DC-DC converter is used to perform DC-DC conversion on the converted power to generate adapter output power. The protocol power delivery interface is used to determine the adapter output power according to a protocol information and control a power path switch to deliver the adapter output power to a power supply pin. The controller determines the converted voltage according to the rectified voltage and the adapter output voltage.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Abstract: A power supply device includes an operating circuit, a circuit measuring device and a computing circuit. The circuit sensing device is configured to continuously sense the operating circuit and obtain a data that varies over time. The computing circuit is coupled to the circuit measuring device. The computing circuit is configured to: receive the data of the operating circuit; provide the data into a deflection model to obtain a simulated temperature of the operating circuit; and determine whether the operating circuit is abnormal according to the simulated temperature. The deflection model is established through a deflection operation according to a plurality of physical parameters of the operating circuit.

Abstract: A compound of Formula (I): Each of R1 to R8 and RA is defined herein. Also disclosed are a composition containing such a compound and a method of treating cancer using the compound.

Abstract: Alignment of devices formed on substrates that are to be bonded may be achieved through the use of scribe lines between the devices, where the scribe lines progressively increase or decrease in size from a center to an edge of one or more of the substrates to compensate for differences in the thermal expansion rates of the substrates. The devices on the substrates are brought into alignment as the substrates are heated during a bonding operation due to the progressively increased or decreased sizes of the scribe lines. The scribe lines may be arranged in a single direction in a substrate to compensate for thermal expansion along a single axis of the substrate or may be arranged in a plurality of directions to compensate for actinomorphic thermal expansion.

Abstract: A light guide plate includes a light incident surface, a first surface connected to the light incident surface, and a plurality of optical microstructures disposed on the first surface. Each optical microstructure has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction perpendicular to the first direction. The first cross-sectional profile is different from the second cross-sectional profile. The optical microstructures include a plurality of first optical microstructures and a plurality of second optical microstructures. The second cross-sectional profile of each first optical microstructure is different from the second cross-sectional profile of each second optical microstructure. A light source module including the light guide plate projects light into the light incident surface.

Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) ?wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.

Abstract: A personnel detection method via millimeter-wave (mmWave) radars is disclosed. A mmWave radar is activated to emit radar waves to scan an indoor area. It is determined whether a bilateral head-shoulder difference of a human body is within a first angle, if so, it is determined whether a unilateral and bilateral head-shoulder difference of the human body is greater than the first angle and between a second angle and a third angle, and, if so, it is determined whether a reflection amount of a relative area of a head and shoulders is within a preset value. If the reflection amount is within the preset value, movement trajectories of a head and shoulder difference of the human body within the preset value is sampled. Thus, the number of people based on the sampled movement trajectories is determined.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A method for managing an anti-accidental touch function and an electronic device are provided. The method includes: providing an accidental touch management interface, in which the anti-accidental touch management interface includes an anti-accidental touch management item and a plurality of anti-accidental touch items; when a touch panel of the electronic device is in a locked state, determining whether the anti-accidental touch management item is enabled; and in response to determining that the anti-accidental touch management item is enabled, performing a first anti-accidental touch function corresponding to an enabled first anti-accidental touch item among the plurality of anti-accidental touch items on the touch panel.

Abstract: A method for regulating immunity and/or inhibiting dendritic cell maturation is provided, especially for treating an allergic disease, treating an autoimmune disease, and/or preventing an organ transplant rejection. Also provided is a combination for preparing tolerogenic dendritic cells, comprising (1) an amino acid-chelated zinc, and (2) a dendritic cell medium.

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.