Patents by Inventor Yu-Lin Yang

Yu-Lin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250148271
    Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.
    Type: Application
    Filed: October 15, 2024
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Po-Chao Tsao, Hsiang-An Chen, Chin-Wei Lin, Ming-Cheng Lee, Tung-Hsing Lee
  • Publication number: 20250148273
    Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 8, 2025
    Inventors: Khim Jun Koh, Chi-Ming Lee, Yi-Ju Ting, Chung-Kai Chang, Po-Chao Tsao, Chin-Wei Lin, Yu-Lin Yang, Tung-Hsing Lee, Chin-Tang Lai
  • Publication number: 20250120138
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lin YANG, Chao-Ching CHENG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Patent number: 12211895
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lin Yang, Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 12199189
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure also includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a sidewall surface of the S/D structure is aligned with a sidewall surface of the first oxide layer.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hou-Yu Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Lin Yang, I-Sheng Chen
  • Publication number: 20240350564
    Abstract: A composition with NRF mitochondria activating ingredient has telomere extension, anti-aging and cell-rejuvenating effects, including salvia miltiorrhiza extract, wheat ?-amylase inhibitor, and probiotic powder. After taken by users, the composition reaches a health effect by extending the telomere length and to reduce the cell age and get younger.
    Type: Application
    Filed: April 19, 2023
    Publication date: October 24, 2024
    Inventor: Yu-Lin Yang
  • Publication number: 20240297101
    Abstract: A packaging method, includes: providing a continuous multi-package structure, which includes a lead frame and a molding layer formed on the lead frame, wherein the lead frame includes a plurality of recesses formed on a bottom surface on a side of the lead frame opposite to the molding layer; forming a coating layer on the bottom surface, to cover the bottom surface and the recesses on the bottom surface; and mechanically cutting the continuous multi-package structure through the recesses, to separately form a plurality of packaging units, wherein in each of the packaging units, an exposed portion of the lead frame exposed in the recesses includes a step shape.
    Type: Application
    Filed: April 27, 2023
    Publication date: September 5, 2024
    Inventors: Yu-Lin Yang, Ming-Chih Hsu, Chun-Hao Chang
  • Publication number: 20240230755
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 4, 2023
    Publication date: July 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Patent number: 11798989
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 11777008
    Abstract: A gate-all-around structure is provided. The gate-all-around structure includes a plurality of nanostructures stacked over a substrate in a vertically direction, and the nanostructures extends from a gate region to a source/drain (S/D) region. The gate-all-around structure includes a gate structure formed in the gate region around the first nanostructures, and a S/D structure formed in the S/D region. The S/D structure is in direct contact with a top surface of one of the nanostructures.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, I-Sheng Chen, Tzu-Chiang Chen
  • Patent number: 11749942
    Abstract: A magnetic connector includes a first insulating housing, a printed circuit board, a plurality of magnetic bodies, a plurality of terminals and a second insulating housing. The first insulating housing has a bottom wall, a side wall, a recess being defined between the bottom wall and the side wall. The printed circuit board is received in the recess. The magnetic bodies are mounted to the printed circuit board. The terminals are mounted to the printed circuit board. The second insulating housing is mounted to the top of the first insulating housing and is covered the recess. The magnetic bodies and the terminals are exposed from a top surface of the second insulating housing. As described above, the magnetic bodies are mounted to the printed circuit board, and then the magnetic bodies are magnetized. Hence, manufacture cost of the magnetic connector is saved.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: September 5, 2023
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventor: Yu-Lin Yang
  • Publication number: 20230268418
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-sheng YUN, Yu-Lin YANG
  • Patent number: 11677010
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chen-Feng Hsu, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 11652141
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20230061138
    Abstract: A semiconductor device structure includes a semiconductor substrate, a first device formed in the first region of the semiconductor substrate and a second device formed in the second region of the semiconductor substrate. The first device includes a first gate structure on the semiconductor substrate. The first gate structure includes a first gate dielectric layer on the semiconductor substrate and a first gate layer on the first gate dielectric layer. The second device includes a second gate structure on the semiconductor substrate. The second gate structure includes a second gate dielectric layer on the semiconductor substrate and a second gate layer on the second gate dielectric layer. The first gate dielectric layer of the first device and the second gate dielectric layer of the second device have different dielectric material compositions.
    Type: Application
    Filed: August 2, 2022
    Publication date: March 2, 2023
    Inventors: Yu-Lin YANG, Ming-Cheng LEE, Yuan-Fu CHUNG
  • Patent number: 11594615
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 11581421
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Publication number: 20230041436
    Abstract: A magnetic connector includes a first insulating housing, a printed circuit board, a plurality of magnetic bodies, a plurality of terminals and a second insulating housing. The first insulating housing has a bottom wall, a side wall, a recess being defined between the bottom wall and the side wall. The printed circuit board is received in the recess. The magnetic bodies are mounted to the printed circuit board. The terminals are mounted to the printed circuit board. The second insulating housing is mounted to the top of the first insulating housing and is covered the recess. The magnetic bodies and the terminals are exposed from a top surface of the second insulating housing. As described above, the magnetic bodies are mounted to the printed circuit board, and then the magnetic bodies are magnetized. Hence, manufacture cost of the magnetic connector is saved.
    Type: Application
    Filed: September 29, 2021
    Publication date: February 9, 2023
    Inventor: YU-LIN YANG
  • Patent number: D1050049
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: November 5, 2024
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventor: Yu-Lin Yang