Patents by Inventor Yu Lin
Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240113099Abstract: An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.Type: ApplicationFiled: April 28, 2023Publication date: April 4, 2024Inventors: Chia-Lin HSU, Yu-Ti SU
-
Publication number: 20240108592Abstract: Provided is a method for treating cancer by administering to a subject in need thereof with a pharmaceutical composition including a benzenesulfonamide derivative in combination with a cancer immunotherapeutic agent such as the immune check point inhibitor (ICI).Type: ApplicationFiled: September 19, 2023Publication date: April 4, 2024Applicant: Gongwin Biopharm Co., LtdInventors: Shun-Chi WU, Chuan-Ching YANG, Zong-Yu YANG, Chia-En LIN, Mao-Yuan LIN
-
Publication number: 20240111116Abstract: An anti-twist structure of voice coil motor includes a base, a lens housing, an elastic sheet, a magnet, and a yoke member. The lens housing has a margin wall, and the margin wall has a first protrusion and a contact portion. The elastic sheet has a hollowed slot, and the first protrusion pass through the hollowed slot, so that the elastic sheet is disposed on a portion of the margin wall and on the contact portion. The yoke member has an upper wall and a side wall. The side wall is disposed at one side of the upper wall and the side wall extends outward in a direction not parallel to the upper wall. The yoke member surrounds the lens housing, the elastic sheet, and the magnet. The lens housing has a deflectable angle relative to a horizontal reference line.Type: ApplicationFiled: December 7, 2023Publication date: April 4, 2024Applicant: Lanto Electronic LimitedInventors: Wen-Yen Huang, Meng-Ting Lin, Fu-Yuan Wu, Shang-Yu Hsu, Bing-Bing Ma, Jie Du
-
Publication number: 20240107986Abstract: A fish identification method is provided. The fish identification method includes capturing an image through a processor, wherein the image includes a fish image. The fish identification method includes identifying a plurality of feature points of the fish image through a coordinate detection model and obtaining a plurality of sets of feature-point coordinates. Each of the plurality of sets of feature-point coordinates corresponds to each of the plurality of feature points. The fish identification method further includes calculating a body length or an overall length of the fish image according to the plurality of sets of feature-point coordinates of the image.Type: ApplicationFiled: January 13, 2023Publication date: April 4, 2024Inventors: Zhe-Yu LIN, Chih-Yi CHIEN, Chen Wei YANG, Tsun-Hsien KUO
-
Publication number: 20240113061Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.Type: ApplicationFiled: December 5, 2023Publication date: April 4, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
-
Publication number: 20240114116Abstract: A multi-projector system and a method of calibrating the multi-projector system are provided. The method includes: controlling a first projector to project a first image, and capturing and generating a first captured image including the first image to obtain a first color value from the first captured image through an image capturing device; projecting a second image according to a first projection parameter, and capturing and generating a second captured image including the second image to obtain a second color value from the second captured image through the image capturing device, wherein the first projection parameter includes an electrical parameter of a light source module of the second projector; calculating an absolute difference between the first color value and the second color value; and adjusting the first projection parameter to update the absolute difference in response to the absolute difference being greater than a first threshold.Type: ApplicationFiled: September 25, 2023Publication date: April 4, 2024Applicant: Coretronic CorporationInventors: Xuan-En Fung, Chun-Lin Chien, Yu-Wen Lo, Yu-Hua Yang
-
Publication number: 20240113202Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
-
Publication number: 20240111210Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: May 9, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
-
Patent number: 11948281Abstract: Methods and systems are provided for accurately filling holes, regions, and/or portions of high-resolution images using guided upsampling during image inpainting. For instance, an image inpainting system can apply guided upsampling to an inpainted image result to enable generation of a high-resolution inpainting result from a lower-resolution image that has undergone inpainting. To allow for guided upsampling during image inpainting, one or more neural networks can be used. For instance, a low-resolution result neural network (e.g., comprised of an encoder and a decoder) and a high-resolution input neural network (e.g., comprised of an encoder and a decoder). The image inpainting system can use such networks to generate a high-resolution inpainting image result that fills the hole, region, and/or portion of the image.Type: GrantFiled: May 1, 2020Date of Patent: April 2, 2024Assignee: Adobe Inc.Inventors: Zhe Lin, Yu Zeng, Jimei Yang, Jianming Zhang, Elya Shechtman
-
Patent number: 11945315Abstract: Techniques are disclosed for systems and methods associated with a powertrain for a micro-mobility fleet vehicle. The fleet vehicle may include at least one drive wheel to provide tractive contact between the flee vehicle and a road surface, an electric motor mechanically coupled to the drive wheel and configured to provide motive force for the fleet vehicle, a brake resistor configured to provide dynamic braking of the motor, and a motor controller electronically coupling the brake resistor to the motor. The motor controller may be configured to control the motive force provided by the motor using the brake resistor. The motor controller may be configured to limit a speed, power, and/or acceleration of the motor using the brake resistor based on an operational environment of, and/or on a directive received by, the fleet vehicle. The brake resistor may provide a relatively wide range of traction control for the fleet vehicle.Type: GrantFiled: December 17, 2019Date of Patent: April 2, 2024Assignee: Lyft, Inc.Inventors: Conrad Xavier Murphy, Chen-Yu Lin, Nikola Popov, Simon Roy
-
Patent number: 11948627Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
-
Patent number: 11947395Abstract: A foldable display device is provided by the present disclosure. The foldable display device includes a foldable display panel and a foldable cover. The foldable cover is adhered to the foldable display panel. The foldable cover includes an inner substrate, an outer substrate and a first adhesive. The first adhesive is disposed between the inner substrate and the outer substrate. A thickness of the first adhesive is ranged from 1 micrometer to 40 micrometers, and a ratio of the sum of the thickness of the first adhesive and a thickness of the inner substrate to a thickness of the foldable cover is greater than or equal to 0.5 and less than 1. In addition, the foldable display device further includes a second adhesive disposed between the foldable display panel and the foldable cover.Type: GrantFiled: October 27, 2020Date of Patent: April 2, 2024Assignee: InnoLux CorporationInventors: Yuan-Lin Wu, Yu-Chia Huang, Kuan-Feng Lee
-
Patent number: 11950431Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.Type: GrantFiled: December 2, 2022Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
-
Patent number: 11950513Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.Type: GrantFiled: July 5, 2022Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
-
Patent number: 11950408Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.Type: GrantFiled: March 7, 2022Date of Patent: April 2, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin
-
Patent number: 11950043Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.Type: GrantFiled: November 18, 2022Date of Patent: April 2, 2024Assignee: LUXSHARE-ICT CO., LTD.Inventors: Shr-Min Chen, Ta-Yu Lin
-
Patent number: 11947180Abstract: An optical system is provided. The optical system includes a first movable portion, a fixed portion, a first driving assembly, and a first sensing assembly. The first movable portion is used for connecting to an optical assembly having a main axis. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The first sensing assembly is used for sensing the movement of the first movable portion relative to the fixed portion.Type: GrantFiled: December 24, 2020Date of Patent: April 2, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chen-Hsien Fan, Yueh-Lin Lee, Yu-Chiao Lo
-
Patent number: 11947251Abstract: An illumination system provides an illumination beam and includes a red light source, a green light source, a blue light source, a first supplementary light source, a first X-shaped light-splitting assembly, a first light-splitting element, and a light-uniforming element. The red light source provides a red beam. The green light source provides a green beam. The blue light source provides a blue beam. The first supplementary light source provides a first supplementary beam. The first X-shaped light-splitting assembly guides the first supplementary beam and the blue beam to the first light-splitting element. The first light-splitting element guides the red beam, the green beam, the blue beam, and the first supplementary beam to the light-uniforming element. The first supplementary beam is a red supplementary beam or a blue supplementary beam, and the illumination system includes at least five light-emitting elements. A projection apparatus including the above illumination system is also provided.Type: GrantFiled: March 23, 2022Date of Patent: April 2, 2024Assignee: Coretronic CorporationInventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
-
Patent number: 11947212Abstract: An electronic device which is capable of being bent in a first direction and includes a plurality of light-emitting units and a plurality of conductive patterns overlapping with at least a portion of the plurality of light-emitting units and extending in a second direction. The first direction and the second direction have an angle ? of not greater than 30 degrees.Type: GrantFiled: January 21, 2021Date of Patent: April 2, 2024Assignee: InnoLux CorporationInventors: Yuan-Lin Wu, Yu-Chia Huang, Yu-Ting Huang, Kuan-Feng Lee, Chia-Hung Hsieh
-
Patent number: D1021153Type: GrantFiled: May 22, 2023Date of Patent: April 2, 2024Assignee: Worthington Armstrong VentureInventors: Nicholas Shaffer, Yu Lin, Joshua L. Neal, Jason Robbins, Dustin Hostetter