Abstract: A wheel rim having a reinforcement structure is disclosed. The wheel rim has two connected side walls and a connecting wall. An outer peripheral edge is connected to each side wall. Either end of the connecting wall is connected to a connecting edge. The outer peripheral edge intersects the connecting edge. A joint portion is formed at an intersection of the connecting wall and the connecting edge. The joint portion is spaced from the corresponding side wall. A reinforcement edge is connected between each side wall and the connecting wall. A hollow support region is enclosed by the corresponding side wall, the outer peripheral edge, the connecting edge, the connecting wall and the reinforcement edge. The joint portion and the side wall do not concentrate external force on the side wall, thereby achieving the effect of reducing the external force acting on the wheel rim and dispersing the force.

Abstract: A method for manufacturing a flip-chip light emitting diode includes providing a first substrate; performing an epitaxial process to form a semiconductor structure on the first substrate, and the semiconductor structure includes a current conductive layer with a bonding surface and defines a first electrode projection area and a second electrode projection area; performing a diffusion process toward the bonding surface by a diffusion material to form at least one path area with a high doping concentration in the current conductive layer; performing a bonding process to bond a second substrate to the bonding surface; and removing the first substrate and forming a first electrode and a second electrode on a side of the semiconductor structure adjacent to the first substrate. A position of the first electrode corresponds to the first electrode projection area, and a position of the second electrode corresponds to the second electrode projection area.

Abstract: An optoelectronic device includes a semiconductor stack, including a first semiconductor layer, an active layer, and a second semiconductor layer; a contact electrode formed on the second semiconductor layer; an insulating reflective structure covering the contact electrode and including a plurality of insulating reflective structure openings to expose the contact electrode; a metal reflective structure covering the plurality of insulating reflective structure openings to electrically connect to the contact electrode; and an insulating structure including one or more first insulating structure openings to expose the first semiconductor layer and one or more second insulating structure openings to expose the metal reflective structure.

Abstract: A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A number theoretic transform operation circuit includes first and second number theoretic transform units and k operation units. The first number theoretic transform unit receives 2k first coefficients in parallel and transforms an order thereof to output 2k second coefficients in parallel. k is a positive integer. The second theoretic transform unit receives 2k third coefficients in parallel and transforms an order thereof to output 2k fourth coefficients in parallel. The k operation units are coupled in parallel between the first and second number theoretic transform units and receive the 2k second coefficients to execute a polynomial operation and output the 2k third coefficients. Each k operation unit sequentially receives two of the 2k second coefficients to execute the polynomial operation and outputs two of the 2k third coefficients. Each operation unit includes a multiplier, two Boolean operation elements, two multiplexers, an adder, and a subtractor.

Abstract: A cathode for rare earth molten salt electrolysis is provided. The cathode includes a column. The bottom of the column includes a cone. The peak of the cone includes a sharp tip or a flat surface. When the peak of the cone is the sharp tip, an opening angle of the sharp tip is between 5 degree and 175 degree. An electrolysis system having a cathode is also provided.

Abstract: A memory device includes a first transistor and a second transistor. Each of the first and second transistors includes a first source/drain electrode, a second source/drain electrode, a channel feature, a gate dielectric and a gate electrode. The second source/drain electrode is coplanar with the first source/drain electrode. The channel feature is disposed between and interconnects the first and second source/drain electrodes. The gate dielectric is disposed over the channel feature. The gate electrode is disposed over the gate dielectric, and overlaps the channel feature. The second transistor is disposed over the first transistor. The first source/drain electrode of the second transistor is connected to the gate electrode of the first transistor.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: The embodiments of the disclosure provide a method for hand tracking. The method includes following steps. A first image of a hand is obtained through a head-mounted device. A first pose of a first part of the hand is determined through a processor based on the first image. A second image of the hand is obtained through a hand-held device. A second pose of a second part of the hand is determined through a processor based on the first image. The first part and the second part complementarily form an entirety of the hand. A gesture of the hand is determined through the processor based on the first pose and the second pose.

Abstract: A blur object detection system includes a memory, an image capturing device, and a processor. The image capturing device is configured to capture a dynamic image, in which the dynamic image includes a blur object and a general object. The processor is coupled to the image capturing device and the memory, and configured to simultaneously or non-simultaneously perform image compression, blur object detection, and general object detection based on the dynamic image to obtain an image compression file, a blur object position of the blur object in the dynamic image, and a general object position of the general object in the dynamic image, and store the image compression file, the blur object position, and the general object position to the memory.

Abstract: A semiconductor device having an integrated lid structure is provided. The method includes mounting a semiconductor die within a cavity of a lid structure. An active side of the semiconductor die is substantially coplanar with a bottom surface of the lid structure. An encapsulant substantially fills a gap region between sidewalls of the semiconductor die and inner sidewall surfaces of the cavity.

Abstract: A light-emitting device comprises a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit comprises a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first light-emitting unit comprises a first semiconductor mesa and a first surrounding part surrounding the first semiconductor mesa, and the second light-emitting unit comprises a second semiconductor mesa and a second surrounding part surrounding the second semiconductor mesa; a trench formed between the first light-emitting unit and the second light-emitting unit and exposing the substrate; a first insulating layer comprising a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and a connecting electrode comprising a first connecting part on the first

Abstract: A semiconductor device having dismantlable structure is provided. The method includes forming a packaged semiconductor die by mounting the semiconductor die onto a package substrate in a flip chip orientation, attaching an interposer substrate over a backside of the semiconductor die, and encapsulating with an encapsulant the semiconductor die and remaining gap region between the package substrate and the interposer substrate. A bond pad of the semiconductor die is interconnected with a conductive trace of the package substrate. The interposer substrate includes a plurality of conductive pads exposed at a top surface and interconnected with the package substrate. A dismantlable structure is attached on the top surface of the interposer substrate. A first region of the dismantlable structure covers the plurality of conductive pads.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.

Abstract: The invention relates to a light emitting diode, which comprises a substrate and a semiconductor epitaxy structure. The semiconductor epitaxial structure is disposed on the substrate. The semiconductor epitaxial structure comprises semiconductor composite layers and a plurality of current spreading layers which are disposed among the semiconductor composite layers. The doping concentrations of the upper and lower adjacent current spreading layers are alternately high and low.

Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.