Abstract: A transparent electronic device includes an organic film, an amorphous transparent oxycarbide layer, and a matrix layer. The organic film includes a polymer containing carboxyl groups (—COOH). The amorphous transparent oxycarbide layer is disposed on the organic film and consists of a metal element, carbon element, oxygen element and an additional element. The metal element is selected from molybdenum (Mo), indium (In), tin (Sn), zinc (Zn), cadmium (Cd) and a combination thereof. An atomic number percentage of the additional element is equal to or greater than 0%, and is less than the least of an atomic number percentage of the metal element, an atomic number percentage of the oxygen element and an atomic number percentage of the carbon element. The matrix layer is disposed on the amorphous transparent oxycarbide layer. A manufacturing method of a transparent electronic device is also provided.

Abstract: A method for processing a curved plastic panel is to first form a hard coating layer, an optical function layer, and a printing layer on a flat plastic substrate, and then cut it into a predetermined shape, and then use a hot pressing and curving device to perform a hot pressing and curving process to the flat plastic substrate in order to make it becoming a curved plastic substrate. The hot pressing and curving device can simultaneously perform hot pressing during the heating process, and has the functions of real-time monitoring of the local temperature and the local curvature forming state, and then feedback to the local heating and curvature forming mechanism for adjustments. The monitoring of temperature and curvature can be divided into multiple stages, which can be monitored stage by stage and adjusted for heating or curvature forming to improve production yield.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A temperature control circuit for an electronic device is provided. The temperature control circuit includes a temperature detector, a status detection circuit and a control circuit. The temperature detector is configured to detect a temperature of the electronic device and generate first evaluation information. The status detection circuit is configured to detect a work status of at least one circuit module in the electronic device and generate second evaluation information. The control circuit is configured to adjust at least one electronic parameter of the electronic device according to the first evaluation parameter and the second evaluation parameter to control the temperature of the electronic device.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A method of detecting a connection fault of an electric motor, applies to a driving mechanism of an inverter, and includes: measuring a three-phase stator current of the electric motor; transforming the three-phase stator current to acquire dual-axis current components in a stationary coordinate; calculating an angle of rotation of the electric motor according to the dual-axis current components; calculating an angular velocity according to the angle of rotation; comparing a frequency of the angular velocity with a frequency of an output voltage of the inverter; and determining that the electric motor occurs a connection fault if a difference between the frequency of the angular velocity and the frequency of the output voltage is greater than a predetermined frequency difference value.

Abstract: A plate member for a cell stack, a cell stack assembly, a method of forming a plate member for a cell stack and a method of assembling a cell stack may be provided, and the plate member includes a channel sheet with at least one peak and one trough for forming fluid flow channels; two alignment parts, each alignment part including a main body and one or more alignment members or holes, the main body having a through hole provided within the main body; and wherein the alignment part is capable of aligning the channel sheet parallel to a plane of the main body and the alignment member is capable of aligning the alignment member to another corresponding alignment member along an axis passing through the alignment member; and further wherein the channel sheet is disposed between the two alignment parts.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a material layer over a semiconductor substrate; forming a plurality of spacer masks over the material layer; patterning the material layer into a plurality of masks below the spacer masks, wherein patterning the material layer comprises an atomic layer etching (ALE) process; and etching the semiconductor substrate through the masks.

Abstract: A semiconductor device may include a single-photon avalanche diode (SPAD) arranged for illumination at a back surface of a substrate. The semiconductor device may include a full deep trench isolation (FDTI) structure between the SPAD and a neighboring SPAD of the semiconductor device. The FDTI may be associated with isolating the SPAD from the neighboring SPAD. The FDTI structure may include a shallow trench isolation (STI) element at the back surface of the substrate. The FDTI structure may include a deep trench isolation (DTI) element at a front surface of the substrate.

Abstract: Provided is a memory cell including a channel material contacting a source line and a bit line; a ferroelectric (FE) material contacting the channel material; and a word line contacting the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer; and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: An electronic device includes an outer housing, a touch display module, and at least one optical assembly. The outer housing has an accommodating portion and an engaging portion. The touch display module is disposed in the accommodating portion and engaged with the engaging portion. The touch display module includes a thin-film transistor substrate, a color filter substrate, and a touch electrode layer. The color filter substrate is disposed on a side of the thin-film transistor substrate facing the outer housing. The touch electrode layer is disposed between the thin-film transistor substrate and the color filter substrate. The optical assembly is disposed on a side of the color filter substrate away from the thin-film transistor substrate.

Abstract: A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

Abstract: A method and apparatus for video coding are disclosed. According to this method, a current block is received at an encoder side or compressed data comprising the current block is received at a decoder side, where the current block is partitioned into two geometric prediction units. Motion information for the two geometric prediction units is determined. Weighting information for the two geometric prediction units is determined. A motion storage type variable based on the weighting information is determined, where the motion information associated with the current block is stored according to a value of the motion storage type variable. A geometric predictor for the current block is generated by blending two geometric predictors according to the weighting information, where the two geometric predictors are derived for the two geometric prediction units using the motion information associated with the current block.

Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A method for signaling adaptive loop filter (ALF) settings is provided. A video decoder receives data from a bitstream for a block of pixels to be decoded as a current block of a current picture of a video. The video decoder parses whether to use adaptive parameter set (APS) for filtering the current block without determining whether to select a particular APS from a plurality of APSs. When the APS is used to filter the current block, the video decoder parses a first filter selection index for selecting a filter from a set of filters in the APS. When the APS is not used to filter the current block, the video decoder signals a second filter selection index for selecting a filter from a set of default fixed filters. The video decoder filters the current block based on the selected filter. The video decoder outputs the filtered current block.

Abstract: The present invention provides novel pharmaceutical formulations comprising derivatives of NDGA, including M4N (tetra-0-methyl nordihydroguaiaretic acid) and temozolomide and their use in the inhibition and treatment of neoplastic diseases, including glioblastoma multiforme, lung and other cancers.

Abstract: A multi-shot moulding part structure includes a first structural part, an ink decoration layer, and a second structural part. The first structural part has a first area surface, a second area surface, and a joining surface located on the second area surface. The joining surface is non-parallel to the second area surface. The ink decoration layer is spread on the first area surface and the second area surface, but not on the joining surface. The second structural part is combined with the first structural part and covers the second area surface. The second structural part touches the joining surface. By the second structural part touching the joining surface of the first structural part that is not coated with the ink decoration layer, the structural bonding strength between the first structural part and the second structural part is enhanced.