Abstract: A method of processing a received message includes: receiving a message through a receiving terminal to obtain the received message; for each bit in the received message, determining a bit state of the bit according to a bit value of the bit; selectively changing the bit state of each bit according to at least a weighting vector and a current value of a flipping threshold, wherein the bit state has a plurality of change ranges; selectively flipping the bit according to the bit state; and adjusting the current value of the flipping threshold according to a number of times the bit has been flipped within a period of time, whether when the number of times the bit has been flipped within the period of time exceeds an upper limit, the flipping threshold adjustment unit increases the current value of the flipping threshold.

Abstract: A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.

Abstract: The present invention provides a decoding method, wherein the decoding method includes the steps of: reading a codeword from a flash memory module; and utilizing a parity check matrix to decode the codeword, wherein the parity check matrix includes a plurality of circulant permutation matrixes, and an order of a parallel calculation of the decoding step is less than a row number of any one of the circulant permutation matrixes.

Abstract: A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.

Abstract: A method of processing a received message includes: receiving a message through a receiving terminal to obtain the received message; for each bit in the received message, determining a bit state of the bit according to a bit value of the bit; selectively changing the bit state of each bit according to at least a weighting vector and a current value of a flipping threshold, wherein the bit state has a plurality of change ranges; selectively flipping the bit according to the bit state; and adjusting the current value of the flipping threshold according to a number of times the bit has been flipped within a period of time, whether when the number of times the bit has been flipped within the period of time exceeds an upper limit, the flipping threshold adjustment unit increases the current value of the flipping threshold.

Abstract: A method of decoding a received message includes: determining a weighting vector corresponding to at least one bit of the received message according to a syndrome and a parity check matrix; determining a bit state of the bit according to a bit value of the bit; changing the bit state according to the weighting vector and a flipping threshold, wherein a change range of the bit state is variable; and flipping the bit according to the bit state.

Abstract: A method of decoding a received message includes: determining a weighting vector corresponding to at least one bit of the received message according to a syndrome and a parity check matrix; determining a bit state of the bit according to a bit value of the bit; changing the bit state according to the weighting vector and a flipping threshold, wherein a change range of the bit state is variable; and flipping the bit according to the bit state.

Abstract: A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.

Abstract: A decoding method of decoding a received message is provided. The received message includes a plurality of received message block. The decoding method includes: obtaining a first syndrome according to a parity check matrix; producing a first bit flipping vector corresponding to a first received message block of the received message blocks at least according to the first syndrome and the first received message block; generating a second syndrome by updating the first syndrome according to the first bit flipping vector and the parity check matrix; and producing a second bit flipping vector corresponding to a second received message block of the received message blocks according to the second syndrome and the second received message block.

Abstract: A RAID decoding system which performs a Built in Self-Test (BIST) includes: a RAID decoder, including: a storage, for storing a syndrome of a first Reed-Solomon (RS) codeword, a syndrome of a second RS codeword, and parity data of the first RS codeword and the second RS codeword; and an RS decoder which performs decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword. A MUX inputs the first and the second RS codeword to the RS decoder in a first iteration, and inputs the parity data to the RS decoder in following iterations for updating the syndromes of the first and the second RS codeword. The updated syndromes are used to perform error correction on the first RS codeword and the second RS codeword.

Abstract: A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.

Abstract: A low-density parity check (LDPC) decoding apparatus for performing shuffle decoding includes: an input wrapper, for receiving input data and padding the input data; an LDPC decoder, coupled to the input wrapper, for receiving the padded input data, performing a plurality of iterations of LDPC decoding upon the padded input data to generate channel values corresponding to the padded input data, and outputting a hard decision channel value in a final iteration; and an initialization circuit, coupled to the LDPC decoder, for receiving the input data in a first iteration of the plurality of iterations, storing the input data into an ordered set data, and immediately sending the ordered set data to the LDPC decoder.

Abstract: A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.