Abstract: A watermark generating circuit includes: a first computing circuit, for generating a second reference signal according to a computing parameter, an input data and a first reference signal; a second computing circuit, coupled to the first computing circuit, for generating at least one selecting signal to determine an embedding location for a watermark according to the second reference signal; and a register, coupled to the first computing circuit, for registering the second reference signal to transmit the registered second reference signal to the first computing circuit for updating the first reference signal, and for generating the watermark according to the second reference signal.

Abstract: A method of decoding CAVLC transform coefficients encoded from an image uses a plurality of registers for storing coefficients and flags and a plurality of MUX devices for selecting data input for corresponding registers. The method includes receiving transform coefficients including first and second encoded data corresponding to an image, generating a trailing-one coefficient with a sign indicated by the first encoded data together with a flag value corresponding to a status of the trailing-one coefficient, and generating a non-trailing zero coefficient according to the second encoded data together with a flag value corresponding to a status of the non-trailing zero coefficient.

Abstract: A positioning device, used in antenna's testing system, includes a crane, a fastening device, a testing antenna and a laser generator. The crane includes a gearing with a sliding shoe thereon. The fastening device is fixed on the sliding shoe of the crane. The testing antenna is fixed in font of the fastening device. The laser generator is fastened on the fastening device and located on a level different from the testing antenna. The laser generator sends out laser for defining the position of the testing antenna.

Abstract: A watermark generating circuit includes: a first computing circuit, for generating a second reference signal according to a computing parameter, an input data and a first reference signal; a second computing circuit, coupled to the first computing circuit, for generating at least one selecting signal to determine an embedding location for a watermark according to the second reference signal; and a register, coupled to the first computing circuit, for registering the second reference signal to transmit the registered second reference signal to the first computing circuit for updating the first reference signal, and for generating the watermark according to the second reference signal.

Abstract: A data encoding method. First, a data array comprising a plurality of elements is stored in a memory. The number of elements unequal to a predetermined value is counted while elements of the array are stored in the memory. Then, a control module reads elements from the data array, and determines whether the number of read elements unequal to the predetermined value is equal to the counted number. When the number of read elements unequal to the predetermined value is equal to the counted number, the control module stops reading elements from the data array.

Abstract: A method for real-time instruction information tracing for recording the information about a plurality of specific instructions executed by a processor. The method contains the following steps. A trace count value is set to an initial value. A trigger count value is set according to the tracing start point. The trace count value is increased whenever a specific instruction executed by the processor. If the increased trace count value is equal to or larger than the trigger count value, record the instruction information about the specific instruction executed by the processor in a buffer; if the buffer is full, stop running the program and output the instruction information stored in the buffer. During this time reset the trigger count value according to the trace count value, reset the trace count value as the initial value, and then start running the program with the processor again.

Abstract: A method and apparatus to reduce the system load of motion estimation for DSP discloses circular buffers, a plurality of absolute difference calculation circuits, a multiple input adder, a full adder, a plurality of accumulators, and a control circuit. The first four bytes from the reference block buffer and the first four bytes from the search window buffer are sent to the four absolute difference calculation circuits. The control circuit determines which of the accumulators requires incrementing the value already in that accumulator by the current output of the multiple input adder. A new set of bytes from the search window buffer is then sent to the absolute difference calculation circuits, a new sum is calculated, and a second accumulator is incremented by the new sum. When all accumulators have been updated, new reference block data used. Each byte of data is loaded from memory only once.

Abstract: A method of decoding CAVLC transform coefficients encoded from an image uses a plurality of registers for storing coefficients and flags and a plurality of MUX devices for selecting data input for corresponding registers. The method includes receiving transform coefficients including first and second encoded data corresponding to an image, generating a trailing-one coefficient with a sign indicated by the first encoded data together with a flag value corresponding to a status of the trailing-one coefficient, and generating a non-trailing zero coefficient according to the second encoded data together with a flag value corresponding to a status of the non-trailing zero coefficient.

Abstract: A data encoding method. First, a data array comprising a plurality of elements is stored in a memory. The number of elements unequal to a predetermined value is counted while elements of the array are stored in the memory. Then, a control module reads elements from the data array, and determines whether the number of read elements unequal to the predetermined value is equal to the counted number. When the number of read elements unequal to the predetermined value is equal to the counted number, the control module stops reading elements from the data array.

Abstract: A method for real-time instruction information tracing for recording the information about a plurality of specific instructions executed by a processor from a tracing start point in the history of running a program, wherein the program contains the specific instructions. The method contains the following step.A trace count value is set to an initial value. A trigger count value is set according to the tracing start point. The processor starts running the program. The trace count value is increased whenever a specific instruction executed by the processor. If the increased trace count value is equal to or larger than the trigger count value, record the instruction information about the specific instruction executed by the processor in a buffer; if the buffer is full, stop running the program and output the instruction information stored in the buffer via an output interface.

Abstract: A VLIW processor for executing a sequence of very long instruction words having a plurality of operations to be executed in parallel. The VLIW processor has a plurality of functional units for parallel execution of the operations specified by the VLIW, an instruction register for holding the VLIW, and a condition flag for indicating the results of a comparison operation. The VLIW includes a conditional head and a plurality of slots, each slot including an operational code and any related operands. The conditional head has a plurality of conditional indicators, each conditional indicator uniquely corresponding to one operation and specifying a condition in which the operation is to be executed if the indicated condition exists. A control circuit is connected to the instruction register and the functional units to deliver the operation from the instruction register to the corresponding functional unit for execution when the condition exists.

Abstract: An apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor is provided. The method includes adding the N bits in the N-bit decode information together to form an initial count value, and generating a plurality of register identification (ID) numbers equivalent in number to the initial count value. The register ID numbers correspond to the positions in the N-bit decode information that has a bit value ‘1’. According to the register ID number, a link is created between the plurality of registers corresponding to the register ID numbers and a memory unit so that the memory unit and the registers are free to exchange stored data.

Abstract: A method and apparatus to reduce the system load of motion estimation for DSP discloses circular buffers, a plurality of absolute difference calculation circuits, a multiple input adder, a full adder, a plurality of accumulators, and a control circuit. The first four bytes from the reference block buffer and the first four bytes from the search window buffer are sent to the four absolute difference calculation circuits. The control circuit determines which of the accumulators requires incrementing the value already in that accumulator by the current output of the multiple input adder. A new set of bytes from the search window buffer is then sent to the absolute difference calculation circuits, a new sum is calculated, and a second accumulator is incremented by the new sum. When all accumulators have been updated, new reference block data used. Each byte of data is loaded from memory only once.

Abstract: A VLIW processor for executing a sequence of very long instruction words having a plurality of operations to be executed in parallel. The VLIW processor has a plurality of functional units for parallel execution of the operations specified by the VLIW, an instruction register for holding the VLIW, and a condition flag for indicating the results of a comparison operation. The VLIW includes a conditional head and a plurality of slots, each slot including an operational code and any related operands. The conditional head has a plurality of conditional indicators, each conditional indicator uniquely corresponding to one operation and specifying a condition in which the operation is to be executed if the indicated condition exists. A control circuit is connected to the instruction register and the functional units to deliver the operation from the instruction register to the corresponding functional unit for execution when the condition exists.

Abstract: A high-speed digitally voltage controlled oscillator with 1/N phase resolution, having a load counter, 1/N phase difference generator, a multiplexor, a clock selector, and a load controller. The high-speed digitally voltage controlled oscillator only needs a load counter with an input frequency D+1 (D is far smaller than N) times an output frequency thereof. The phases of first and (M/2+1)th phases of M clock signals with 1/N phase difference (M is far smaller than N) generated by the 1/N phase difference generator are fixed at 0° and 180° with respect to a reference clock. Therefore, only (M/2−1) clock signals are affected by variation of process parameters. Consequently, the high-speed digitally voltage controlled oscillator can tolerate variation error of process parameter and is applicable for high resolution and high frequency operation.

Abstract: A high-speed digitally voltage controlled oscillator with 1/N phase resolution, having a load counter, 1/N phase difference generator, a multiplexor, a clock selector, and a load controller. The high-speed digitally voltage controlled oscillator only needs a load counter with an input frequency D+1 (D is far smaller than N) times an output frequency thereof. The phases of first and (M/2+1)th phases of M clock signals with 1/N phase difference (M is far smaller than N) generated by the 1/N phase difference generator are fixed at 0° and 180° with respect to a reference clock. Therefore, only (M/2−1) clock signals are affected by variation of process parameters. Consequently, the high-speed digitally voltage controlled oscillator can tolerate variation error of process parameter and is applicable for high resolution and high frequency operation.

Abstract: A multi-functional electric fan comprises a U-shaped brace pivotably mounted to motor, a support for supporting the brace, an arcuate guide mechanism hinged to the support, a transmission mechanism having a plurality of gears and an arm secured to a pin through an opening of the guide mechanism, a transverse post, and a vertical post. Thus fan can pivot transversely and longitudinally by the cooperation of posts, gears, pin, and opening at the same time to reciprocally induce air movement in a transverse, longitudinal, wavy, or fixed direction.

Abstract: A coprocessor data access control method having a coprocessor memory access instruction with a coprocessor indicating field such that the quantity of word data to be transmitted between the coprocessor and the memory unit can be determined. The coprocessor indicating field actually includes a coprocessor number field and a coprocessor register field. The coprocessor number field indicates the particular coprocessor to be used while the coprocessor register field indicates the particular registers to be used.

Abstract: A memory data access structure and an access method suitable for use in a processor. For each instruction executed by the processor, the execution results are recognized by the processor and transferred to a cache memory via control signals. When the instruction to be fetched is not stored in the cache memory, according to the control signals, the cache memory can determine whether the instruction is to be fetched from an external memory. With such structure, no matter whether the processor comprises a branch prediction mechanism or not, many operation clock cycles consumed in the processor of the prior art are saved by compensating for the situation that the cache memory fails to fetch, that is, a Miss of the cache memory. The efficiency and performance of the processor can be effectively enhanced.

Abstract: An apparatus and method for executing block data transfer instruction inside a processor. The apparatus is capable of finding out the registers and their corresponding addresses that must be processed from the decode information of a register list. By processing the data in the specified registers only, program code as well as memory access cycles can be reduced and performance of the processor can be improved.