Abstract: A memory data access structure and an access method suitable for use in a processor. For each instruction executed by the processor, the execution results are recognized by the processor and transferred to a cache memory via control signals. When the instruction to be fetched is not stored in the cache memory, according to the control signals, the cache memory can determine whether the instruction is to be fetched from an external memory. With such structure, no matter whether the processor comprises a branch prediction mechanism or not, many operation clock cycles consumed in the processor of the prior art are saved by compensating for the situation that the cache memory fails to fetch, that is, a Miss of the cache memory. The efficiency and performance of the processor can be effectively enhanced.

Abstract: An electrical connector for interconnecting an IC module and a circuit board comprises a base, a slide plate, a plurality of contacts, a spacing plate, a prepreg, a cover and a push plate. A plurality of passageways is formed in the base for receiving corresponding contacts. The slide plate is mounted on a top surface of the base, and a plurality of apertures is formed in the slide plate corresponding to the passageways of the base. The spacing plate is mounted to a bottom surface of the base and forms a plurality of positioning holes for receiving soldering portions of the corresponding contacts. The prepreg is disposed between the base and the spacing plate, and a plurality of spacing holes is formed in the prepreg corresponding to the passageways of the base. Since the spacing plate and the circuit board have the same thermal expansion coefficient, the positioning holes remain in alignment with corresponding solder pads formed on the circuit board during a soldering process.