Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.

Abstract: A method is provided. The method includes applying a first pulse to a ferroelectric memory device, measuring a memory window metric of the ferroelectric memory device, and applying a second pulse to the ferroelectric memory device. The first pulse may have a first voltage magnitude. The second pulse may have a second voltage magnitude. The second voltage magnitude may be determined based at least in part on the measured memory window metric.

Abstract: Provided is a centrifugal heat dissipation fan including a housing and an impeller. The impeller is disposed in the housing. The impeller has a hub and multiple blades disposed surrounding the hub. Every two adjacent blades have different blade structures relative to the housing such that the blade structures pass by a fixed position of the housing and generate blade tones of varying frequencies when the impeller rotates.

Abstract: A semiconductor structure includes a gate layer, a ferroelectric layer, a source structure, a drain structure, an oxide semiconductor and a high-k material layer. The gate layer is disposed in an interconnect structure. The ferroelectric layer is disposed over the gate layer. The source structure and the drain structure are disposed over the ferroelectric layer. The oxide semiconductor is disposed over the ferroelectric layer and between the source structure and the drain structure. The high-k material layer is disposed on and contacts a surface of the ferroelectric layer. A method of manufacturing the semiconductor structure is also provided.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

Abstract: A semiconductor memory structure includes a substrate, a doped region in the substrate, a stack over the substrate, a column disposed over the substrate and penetrating the stack, a ferroelectric layer, and semiconductor layer between the ferroelectric layer and the column. The stack includes a plurality of conductive layers and a plurality of insulating layer alternately stacked. The column includes an isolation structure, a source structure and a drain structure. The semiconductor layer is separated from the substrate by the ferroelectric layer.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than ?.

Abstract: A device is disclosed, including a latch circuit, a first pass-gate transistor, and a second pass-gate transistor. The latch circuit stores a bit data and is arranged in a first layer. The first pass-gate transistor and the second pass-gate transistor are arranged in a second layer separated from the first layer. The first pass-gate transistor is coupled between a first bit line and a first terminal of the latch circuit, and the second pass-gate transistor is coupled between a second bit line and a second terminal of the latch circuit.

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

Abstract: Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

Abstract: A memory device including a memory array, a driver circuit, and a recover circuit is provided. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.

Abstract: A graphics card including a circuit board module, a first heat dissipation fin, and a pair of fans is provided. The circuit board module includes a circuit board and a heat source. The circuit board has first to fourth sides surrounding the heat source. The first and second sides are opposite sides. The third and fourth sides are opposite sides. The first heat dissipation fin is in thermal contact with the heat source and has multiple channels communicating with the first to fourth sides. The fans disposed on the first and second sides respectively have first flow outlets facing the first heat dissipation fin and generate flows towards the first heat dissipation fin through the first flow outlets. The flows meet and squeeze in the channels to form turbulent flows and flow out of the graphics card through the third and fourth sides respectively. A computer host is also provided.