Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.

Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.

Abstract: A power module package structure includes a first substrate and a power component. The first substrate includes at least one conductive layer on a surface thereof. The power component includes a first chip and a first spacer. The first chip has at least one electrode. The first spacer in a heat dissipation space between the first substrate and the first chip includes an insulating heat dissipation layer in the heat dissipation space and multiple vertical conductive connectors, each of the vertical conductive connectors penetrates the insulating heat dissipation layer. The insulating heat dissipation layer surrounds the vertical conductive connectors and electrically isolates the vertical conductive connectors. The vertical conductive connector includes two opposite ends, one end electrically connected to the conductive layer, and the other end electrically connected to the electrode to form a conductive path and a heat dissipation path between the first chip and the first substrate.

Abstract: A semiconductor device includes an insulating layer embedding a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a dielectric compound of silicon, and suppresses loss of metallic elements during subsequent anneal processes.

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

Abstract: A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory including a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source/drain electrode extending on the channel layer; and a second source/drain electrode extending along the channel layer; and a resistive-type memory including a resistive memory layer, wherein the resistive memory layer extends between the second source/drain electrode and the channel layer.

Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.

Abstract: A semiconductor device includes a gate electrode, a gate dielectric located over the gate electrode, a channel layer including a semiconductor material and located over the gate dielectric, blocking layers located over the channel layer, covering portions of channel layer, and spaced apart from each other, buffer layers respectively located over the blocking layers, respectively surrounded by the blocking layers, and including a material that receives hydrogen, and source/drain contacts respectively located over the buffer layers and respectively surrounded by the buffer layers.

Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.

Abstract: A heat dissipation system of portable electronic device includes a body, at least one fan and at least one spacing member. At least one heat source of the portable electronic device is arranged in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet located in the axial direction and at least one flow outlet located in the radial direction. The spacing member is disposed on at least one of the body or the fan to form a stratified air flow in the body along the axial direction. The stratified air flows into the fan through the flow inlet and out of the fan through the flow outlet respectively.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

Abstract: A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.

Abstract: A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.