Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. The first memory array and the second memory array share the same bus. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, and a ferroelectric layer over the gate electrode.

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).

Abstract: A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and a conductive feature disposed in the ILD layer and electrically coupled to the first epitaxial S/D feature and the second epitaxial S/D feature. The conductive feature includes first portions having bottom surfaces contacting the first and the second epitaxial S/D features, and a second portion having a bottom surface contacting the ILD layer. The bottom surface of the second portion is above the bottom surface of the first portions.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than 3/5.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.

Abstract: Field effect transistors and method of making. The field effect transistors include a pair of active regions in a channel layer, a channel region located between the pair of active regions and a self-aligned passivation layer located on a surface of the pair of active regions.

Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.