Patents by Inventor Yu-Ning CHANG

Yu-Ning CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT
    Publication number: 20130019219
    Abstract: System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Yu Chen, Yi-Tang Lin, Cheok-Kei Lei, Hsiao-Hui Chen, Yu-Ning Chang, Hsingjen Wann, Chih-Sheng Chang, Chien-Wen Chen
  • SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN
    Publication number: 20120278776
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.
    Type: Application
    Filed: March 9, 2012
    Publication date: November 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheok-Kei LEI, Yi-Tang LIN, Hsiao-Hui CHEN, Yu-Ning CHANG, Shu-Yu CHEN, Chien-Wen CHEN, Chih-Sheng CHANG, Clement Hsingjen WANN
  • SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN
    Publication number: 20120278777
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
    Type: Application
    Filed: March 9, 2012
    Publication date: November 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Tang LIN, Cheok-Kei LEI, Shu-Yu CHEN, Yu-Ning CHANG, Hsiao-Hui CHEN, Chih-Sheng CHANG, Chien-Wen CHEN, Clement Hsingjen WANN