Patents by Inventor Yu-Piao Wang

Yu-Piao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050045865
    Abstract: A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact-hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having low-erdielectric constant property, the parasitic capacitance can be reduced.
    Type: Application
    Filed: December 8, 2003
    Publication date: March 3, 2005
    Inventor: Yu-Piao Wang
  • Patent number: 6803310
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: October 12, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Patent number: 6787461
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 7, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Patent number: 6686278
    Abstract: A method for forming a plug metal layer is disclosed and includes the following steps. Performance of an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on a barrier layer, wherein the atomic layer deposition comprise: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, being transported on the barrier layer. Next, performance of a purge/vacuum process. Then transporting a reactive gas, such as WF6, to form the continuous metal seed layer (CMSL). A subsequent cycle step of atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) to about 20 to 40 Å.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: February 3, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Patent number: 6680258
    Abstract: An opening through an insulating layer between a first layer and a second layer of a semiconductor device is formed where the second layer is a polysilicon or amorphous silicon hard mask layer. The polysilicon or amorphous silicon hard mask layer is etched to form at least one opening through the polysilicon or amorphous silicon hard mask layer using a patterning layer as a mask having at least one opening. The insulating layer is etched to form the opening through the insulating layer using the etched polysilicon or amorphous silicon hard mask layer as a mask. The etched polysilicon or amorphous silicon hard mask layer is nitridized prior to subsequent processing.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: January 20, 2004
    Assignee: ProMOS Technologies, Inc.
    Inventors: Yuan-Li Tsai, Yu-Piao Wang
  • Publication number: 20030190802
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Applicant: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Publication number: 20030124787
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 3, 2003
    Applicant: United Microelectronics Corp.
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Publication number: 20020192953
    Abstract: Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer; next, perform a purge/vacuum process; then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL); the cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 Å.
    Type: Application
    Filed: June 19, 2001
    Publication date: December 19, 2002
    Inventors: Yu-Piao Wang, Chia-Che Chuang
  • Patent number: 6465348
    Abstract: A MOCVD is performed to form a titanium nitride layer on the surface of a semiconductor substrate. Following that, a pulsed plasma treatment is performed to remove hydro-carbon impurities from the titanium nitride layer. Therein, the pulsed plasma treatment is performed in a pressure chamber comprising nitrogen gas (N2) hydrogen gas (H2) or argon gas (Ar). A pressure of the pressure chamber is controlled to between 1 to 3 Torr, with the power of the pressure chamber controlled to between 500 and 1000 watts.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: October 15, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Yu-Piao Wang