Patents by Inventor Yu-Ping Huang
Yu-Ping Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12043668Abstract: An antibody, or an antigen-binding fragment thereof, that binds specifically to human CSF-1R includes a heavy chain variable domain that contains a HCDR1 region having the sequence of SEQ ID NO: 4, a HCDR2 region having the sequence of SEQ ID NO: 5, and a HCDR3 region having the sequence of SEQ ID NO: 6; and a light chain variable domain that contains a LCDR1 region having the sequence of SEQ ID NO: 7, a LCDR2 region having the sequence of SEQ ID NO: 8, and a LCDR3 region having the sequence of SEQ ID NO: 9. The heavy chain variable domain comprises the sequence of SEQ ID NO: 2, and wherein the light chain variable domain comprises the sequence of SEQ ID NO: 3.Type: GrantFiled: December 13, 2019Date of Patent: July 23, 2024Assignee: DEVELOPMENT CENTER FOR BIOTECHNOLOGYInventors: Chen-Hsuan Ho, Chu-Bin Liao, Yu-Kai Chen, Chen-Wei Huang, Tze-Ping Yang, Szu-Liang Lai
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Publication number: 20240238432Abstract: A method for modifying glycoproteins is provided. The present disclosure also provides a method for producing glycoprotein-payload conjugates, the conjugates produced thereby, and the use thereof.Type: ApplicationFiled: December 29, 2023Publication date: July 18, 2024Inventors: Shih-Hsien CHUANG, Yu-Wei LAI, Cheng-Chou YU, Shu-Ping YEH, Jin-Yu WANG, Shih-Chong TSAI, Wei-Ting SUN, Chin-Yi Huang
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Publication number: 20240243466Abstract: A wireless briefing device includes a first antenna, a second antenna, and a ground plane. Each of the first antenna and the second antenna couples out a frequency band. A distance between the first antenna and the ground plane is between 0.2 and 0.3 times of a wavelength of the frequency band, and a distance between the second antenna and the ground plane is between 0.2 and 0.3 times of the wavelength of the frequency band.Type: ApplicationFiled: June 19, 2023Publication date: July 18, 2024Applicant: BENQ CORPORATIONInventors: Yu-Ping Huang, Chun-Han Lin, Chen-Chi Wu, Chia-Nan Shih, Cheng-Pu Lin
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Patent number: 12040178Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.Type: GrantFiled: April 26, 2023Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Wen Hsueh, Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen
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Publication number: 20240021246Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.Type: ApplicationFiled: May 9, 2023Publication date: January 18, 2024Applicant: eMemory Technology Inc.Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
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Patent number: 11455103Abstract: A cloud secured storage system is provided in a peer-to-peer network that includes a client end and a farm end. A user file is segmented and a hash function is used for encryption to generate a plurality of data chunks together with an Information Dispersal Algorithm. The plurality of data chunks are respectively stored in a plurality of cloud servers. The plurality of cloud servers backup the plurality of data chunks as a backup file. If the data chunk in one of the plurality of cloud servers is lost, the adjacent cloud server transmits the backup file to the cloud server where the data chunk is lost. The cloud secured storage system of the present disclosure successfully stores the user file in the plurality of cloud servers to prevent cyberattacks owing to the process of file segmentation, encryption, backup file, and algorithm.Type: GrantFiled: September 17, 2020Date of Patent: September 27, 2022Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Tsung-Nan Lin, Yu-Ping Huang
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Patent number: 11074963Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.Type: GrantFiled: April 1, 2020Date of Patent: July 27, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
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Publication number: 20210096753Abstract: A cloud secured storage system is provided in a peer-to-peer network that includes a client end and a farm end. A user file is segmented and a hash function is used for encryption to generate a plurality of data chunks together with an Information Dispersal Algorithm. The plurality of data chunks are respectively stored in a plurality of cloud servers. The plurality of cloud servers backup the plurality of data chunks as a backup file. If the data chunk in one of the plurality of cloud servers is lost, the adjacent cloud server transmits the backup file to the cloud server where the data chunk is lost. The cloud secured storage system of the present disclosure successfully stores the user file in the plurality of cloud servers to prevent cyberattacks owing to the process of file segmentation, encryption, backup file, and algorithm.Type: ApplicationFiled: September 17, 2020Publication date: April 1, 2021Inventors: Tsung-Nan Lin, Yu-Ping Huang
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Publication number: 20200365200Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.Type: ApplicationFiled: April 1, 2020Publication date: November 19, 2020Inventors: Yu-Ping HUANG, Chun-Hung LIN, Cheng-Da HUANG
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Patent number: 10644911Abstract: A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.Type: GrantFiled: August 22, 2019Date of Patent: May 5, 2020Assignee: National Chiao Tung UniversityInventors: Wei-Zen Chen, Chia-Tse Hung, Yu-Ping Huang, Yao-Chia Liu
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Patent number: 9407474Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.Type: GrantFiled: September 16, 2015Date of Patent: August 2, 2016Assignee: National Chiao Tung UniversityInventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
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Publication number: 20160080178Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.Type: ApplicationFiled: September 16, 2015Publication date: March 17, 2016Inventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
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Patent number: 8957660Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.Type: GrantFiled: September 11, 2012Date of Patent: February 17, 2015Assignee: Anpec Electronics CorporationInventors: Ke-Horng Chen, Yueh-Lung Kuo, Chih-Heng Su, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee
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Publication number: 20130293203Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.Type: ApplicationFiled: September 11, 2012Publication date: November 7, 2013Applicant: ANPEC ELECTRONICS CORPORATIONInventors: Ke-Horng Chen, Yueh-Lung Kuo, Chih-Heng Su, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee
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Patent number: 6586146Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.Type: GrantFiled: August 31, 2001Date of Patent: July 1, 2003Assignee: United MicroelectronicsInventors: Kun-Yuan Chang, Wang-Hsiang Ho, Yu-Ping Huang, Li-Dar Tsai, Chung-Yung Wu
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Patent number: 6566225Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.Type: GrantFiled: August 6, 2001Date of Patent: May 20, 2003Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hsin-Huei Chen, Yu-Ping Huang
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Patent number: 6548406Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.Type: GrantFiled: August 17, 2001Date of Patent: April 15, 2003Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hsin-Huei Chen, Ying-Tso Chen, Shou-Wei Hwang, Yu-Ping Huang
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Publication number: 20030044700Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.Type: ApplicationFiled: August 31, 2001Publication date: March 6, 2003Inventors: Kun-Yuan Chang, Wang-Hsiang Ho, Yu-Ping Huang, Li-Dar Tsai, Chung-Yung Wu
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Publication number: 20030036275Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.Type: ApplicationFiled: August 17, 2001Publication date: February 20, 2003Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun Lai, Hsin-Huei Chen, Ying-Tso Chen, Shou-Wei Hwang, Yu-Ping Huang
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Publication number: 20030027421Abstract: The present invention mainly provides a method to locally form metal suicides on an integral circuit. The method can avoid forming metal silicides on the surface of those devices with high resistance, so the performance of those devices will not degrade. The method can also avoid a phenomenon of leakage current which is caused by forming metal silicides between the memory cells on the same word line.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ying-Tso Chen, Erh-Kun Lai, Hsin-Huei Chen, Yu-Ping Huang, Shou-Wei Hwang