Patents by Inventor Yu-Ping Huang

Yu-Ping Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250114867
    Abstract: A laser welding method for steel plates and a profile steel welded by laser welding are disclosed. The laser welding method comprises the following steps of connecting a first steel plate and a second steel plate to form a joint; and using a laser to weld the joint to form a profile steel. The laser has a laser power between 10,000 and 25,000 watts. A weld bead is formed at the joint. The weld bead has a weld depth and a weld width. The ratio of the weld depth to the weld width is between 1 and 5. Thus, the process can be simplified effectively, the welding time can be shortened, and the processing area can be reduced.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: LI-WEN LAI, WEI-LUN TSAI, YU-PING HUANG, CHIH-HUI TAI
  • Publication number: 20240275919
    Abstract: A video and audio streaming transmission system is provided. The video and audio streaming transmission system includes a receiving end module, a first transmitting end module and a second transmitting end module. The first transmitting end module obtains a first audio signal, and sends the first audio signal to the receiving end module. The second transmitting end module obtains a second audio signal, and sends the second audio signal to the receiving end module. The receiving end module returns a processed audio signal to the first computer device according to the first audio signal and the second audio signal, so that the first computer device provides the processed audio signal to a conference module.
    Type: Application
    Filed: October 11, 2023
    Publication date: August 15, 2024
    Applicant: BENQ CORPORATION
    Inventors: Chao-Kuang Yen, Yu-Ping Huang, Chen-Chi Wu, Cheng-Pu Lin, Chia-Nan Shih, Jung-Kun Tseng
  • Publication number: 20240243466
    Abstract: A wireless briefing device includes a first antenna, a second antenna, and a ground plane. Each of the first antenna and the second antenna couples out a frequency band. A distance between the first antenna and the ground plane is between 0.2 and 0.3 times of a wavelength of the frequency band, and a distance between the second antenna and the ground plane is between 0.2 and 0.3 times of the wavelength of the frequency band.
    Type: Application
    Filed: June 19, 2023
    Publication date: July 18, 2024
    Applicant: BENQ CORPORATION
    Inventors: Yu-Ping Huang, Chun-Han Lin, Chen-Chi Wu, Chia-Nan Shih, Cheng-Pu Lin
  • Publication number: 20240021246
    Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.
    Type: Application
    Filed: May 9, 2023
    Publication date: January 18, 2024
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11455103
    Abstract: A cloud secured storage system is provided in a peer-to-peer network that includes a client end and a farm end. A user file is segmented and a hash function is used for encryption to generate a plurality of data chunks together with an Information Dispersal Algorithm. The plurality of data chunks are respectively stored in a plurality of cloud servers. The plurality of cloud servers backup the plurality of data chunks as a backup file. If the data chunk in one of the plurality of cloud servers is lost, the adjacent cloud server transmits the backup file to the cloud server where the data chunk is lost. The cloud secured storage system of the present disclosure successfully stores the user file in the plurality of cloud servers to prevent cyberattacks owing to the process of file segmentation, encryption, backup file, and algorithm.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: September 27, 2022
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Tsung-Nan Lin, Yu-Ping Huang
  • Patent number: 11074963
    Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 27, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Publication number: 20210096753
    Abstract: A cloud secured storage system is provided in a peer-to-peer network that includes a client end and a farm end. A user file is segmented and a hash function is used for encryption to generate a plurality of data chunks together with an Information Dispersal Algorithm. The plurality of data chunks are respectively stored in a plurality of cloud servers. The plurality of cloud servers backup the plurality of data chunks as a backup file. If the data chunk in one of the plurality of cloud servers is lost, the adjacent cloud server transmits the backup file to the cloud server where the data chunk is lost. The cloud secured storage system of the present disclosure successfully stores the user file in the plurality of cloud servers to prevent cyberattacks owing to the process of file segmentation, encryption, backup file, and algorithm.
    Type: Application
    Filed: September 17, 2020
    Publication date: April 1, 2021
    Inventors: Tsung-Nan Lin, Yu-Ping Huang
  • Publication number: 20200365200
    Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.
    Type: Application
    Filed: April 1, 2020
    Publication date: November 19, 2020
    Inventors: Yu-Ping HUANG, Chun-Hung LIN, Cheng-Da HUANG
  • Patent number: 10644911
    Abstract: A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 5, 2020
    Assignee: National Chiao Tung University
    Inventors: Wei-Zen Chen, Chia-Tse Hung, Yu-Ping Huang, Yao-Chia Liu
  • Patent number: 9407474
    Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 2, 2016
    Assignee: National Chiao Tung University
    Inventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
  • Publication number: 20160080178
    Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 17, 2016
    Inventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
  • Patent number: 8957660
    Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 17, 2015
    Assignee: Anpec Electronics Corporation
    Inventors: Ke-Horng Chen, Yueh-Lung Kuo, Chih-Heng Su, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee
  • Publication number: 20130293203
    Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.
    Type: Application
    Filed: September 11, 2012
    Publication date: November 7, 2013
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventors: Ke-Horng Chen, Yueh-Lung Kuo, Chih-Heng Su, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee
  • Patent number: 6586146
    Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: July 1, 2003
    Assignee: United Microelectronics
    Inventors: Kun-Yuan Chang, Wang-Hsiang Ho, Yu-Ping Huang, Li-Dar Tsai, Chung-Yung Wu
  • Patent number: 6566225
    Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: May 20, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Hsin-Huei Chen, Yu-Ping Huang
  • Patent number: 6548406
    Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: April 15, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Hsin-Huei Chen, Ying-Tso Chen, Shou-Wei Hwang, Yu-Ping Huang
  • Publication number: 20030044700
    Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventors: Kun-Yuan Chang, Wang-Hsiang Ho, Yu-Ping Huang, Li-Dar Tsai, Chung-Yung Wu
  • Publication number: 20030036275
    Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.
    Type: Application
    Filed: August 17, 2001
    Publication date: February 20, 2003
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsin-Huei Chen, Ying-Tso Chen, Shou-Wei Hwang, Yu-Ping Huang
  • Publication number: 20030027420
    Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a silicon layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Shou-Wei Hwang, Tung-Cheng Kuo, Yu-Ping Huang
  • Publication number: 20030027404
    Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.
    Type: Application
    Filed: August 6, 2001
    Publication date: February 6, 2003
    Applicant: MACRONIX INTERNATIONAL CO., LTD
    Inventors: Erh-Kun Lai, Hsin-Huei Chen, Yu-Ping Huang