Abstract: A process planning apparatus based on augmented reality (AR) includes: a camera set capturing color and depth images of a processing machine and a probe operated by a human user in a real scene; a processor, which is signal-connected to the camera set and the processing machine, creates spatial intelligences for motion planning of the probe operated by the human user in an AR environment that combines a virtual workpiece with the real scene, and generates instructional data from the spatial intelligences to guide the human user to operate the probe to produce machine motion data for a manufacturing task; and an output interface, which is signal-connected to the processor and outputs scene data, the virtual workpiece and the instructional data to the human user.

Abstract: The present disclosure provides a rear structure coupled to a display panel. The rear structure comprises a rear cover comprising a rib structure for supporting the display panel, the rib structure comprising a plurality of horizontal bars, a plurality of vertical bars, and a plurality of blocks, and each of the blocks formed by at least one of the horizontal bars and at least one of the vertical bars. Wherein a first section of the rib structure comprises at least two aligned adjacent horizontal bars and at least two aligned adjacent vertical bars, and a second section of the rib structure comprises at least two non-aligned vertical bars.

Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.

Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.

Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.

Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.

Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.

Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.

Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.

Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a silicon layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: The present invention mainly provides a method to locally form metal suicides on an integral circuit. The method can avoid forming metal silicides on the surface of those devices with high resistance, so the performance of those devices will not degrade. The method can also avoid a phenomenon of leakage current which is caused by forming metal silicides between the memory cells on the same word line.

Abstract: The present invention mainly provides a method to locally form metal silicides on an integral circuit. The method can avoid forming metal silicides on the surface of those devices with high resistance, so the performance of those devices will not degrade. The method can also avoid a phenomenon of leakage current which is caused by forming metal silicide between the memory cells on the same word line.

Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of present invention achieve above objectives by principally using a design rule to adequately arrange elements in proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is previously formed in the spaced region between the two neighboring memory cells and is used as a mask. Thus, in a following selective etching process, a part of silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objectives is achieved.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.