Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.

Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a silicon layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

Abstract: The present invention mainly provides a method to locally form metal silicides on an integral circuit. The method can avoid forming metal silicides on the surface of those devices with high resistance, so the performance of those devices will not degrade. The method can also avoid a phenomenon of leakage current which is caused by forming metal silicide between the memory cells on the same word line.

Abstract: The present invention mainly provides a method to locally form metal suicides on an integral circuit. The method can avoid forming metal silicides on the surface of those devices with high resistance, so the performance of those devices will not degrade. The method can also avoid a phenomenon of leakage current which is caused by forming metal silicides between the memory cells on the same word line.

Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of present invention achieve above objectives by principally using a design rule to adequately arrange elements in proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is previously formed in the spaced region between the two neighboring memory cells and is used as a mask. Thus, in a following selective etching process, a part of silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objectives is achieved.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor is disclosed. The method provides a three dimensional MIM capacitor having upgraded capacitance. A plurality of trenches are formed within the MIM capacitor to increase the charge storage area of the MIM capacitor without occupying additional planar area thereby upgrade the capacitance of the MIM capacitor and the integration.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: A software implementable approach capable of creating, delivering, reassembling, rendering, and storing asynchronous and synchronous multimedia message. This approach integrates video/audio streaming with existing Internet/Intranet e-mail messaging and video/audio conferencing systems. The software provides both one-way asynchronous communication as well as bi-directional synchronous communication. Each stream represents a user access from client on one computer to server on the other computer. The method enables electronic multimedia messaging on video/audio capture-equipped mobile platform with limited pre-installed software capability or memory footprint.

Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

Abstract: A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the STI. A conductive layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses a dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The conductive layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality will not be degraded.