Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract: A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.

Abstract: A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A method of fabricating a metal gate structure is provided. Firstly, a high-K gate dielectric layer is formed on a semiconductor substrate. Then, a first metal-containing layer having a surface away from the gate dielectric layer is formed on the gate dielectric layer. After that, the surface of the first metal-containing layer is treated to improve the nitrogen content thereof of the surface. Subsequently, a silicon layer is formed on the first metal-containing layer. Because the silicon layer is formed on the surface having high nitrogen content, the catalyzing effect to the silicon layer resulted from the metal material in the first metal-containing layer can be prevented. As a result, the process yield is improved.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.

Abstract: A method for forming barrier layers comprises steps of forming a first metal barrier layer covering a first dielectric layer and contacting a conductive layer through a via of the first dielectric layer, forming a barrier layer of metalized materials on the first metal layer, optionally forming a second metal barrier layer on the barrier layer of metalized materials, removing portions of the barrier layer of metalized materials above the via bottom in the first dielectric layer, and leaving the barrier layer of metalized materials remaining on the via sidewall in the first dielectric layer; and forming a second metal layer covering the barrier layer of metalized materials. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A capacitor structure has a first electrode and a second electrode, which does not electrically connect to the first electrode. The first electrode has a plurality of first meshed conductive structures. The first meshed conductive structures have the same layout pattern, and are electrically connected to each other. The second electrode has a plurality of second meshed conductive structures. The second meshed conductive structures have the same layout pattern, and are electrically connected to each other. The first meshed conductive structures and the second meshed conductive structures are alternately stacked.

Abstract: A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.

Abstract: A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A barrier layer structure includes a first dielectric layer forming on a conductive layer and having a via being formed in the first dielectric layer, wherein the via in the first dielectric layer is connected to the conductive layer. A first metal layer is steppedly covered on the first dielectric layer. A layer of metallized materials is steppedly covered on the first metal layer, but the layer of metallized materials does not cover the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. A second metal layer is steppedly covered on the layer of metallized materials, and the second metal layer is covered the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. The barrier layer structure will have lower resistivity in the bottom via of the first dielectric layer and it is capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.

Abstract: A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.

Abstract: A method of forming at least one wire on a substrate. The substrate includes at least one conductive region. An insulating layer is disposed on the substrate. At least one recess in the insulating layer exposes the conductive region. A barrier layer is formed on a surface of the insulating layer and the recess first. A continuous and uniform conductive layer is then formed on a surface of the barrier layer. A seed layer is thereafter formed on a surface of the conductive layer. Finally, a metal layer filling up the recess is formed on a surface of the seed layer.

Abstract: A method for forming barrier layers comprises: first, forming a dual damascene structure on a metal layer of a wafer. The dual damascene structure includes a first dielectric layer and a second dielectric layer. There is a via in the first dielectric layer and there is a trench in the second dielectric layer; second, forming a first tantalum metal layer on the dual damascene structure; third, forming a tantalum nitride layer on the first tantalum metal layer, removing the tantalum nitride layer in the via bottom of the first dielectric layer with a ion-sputtering way and the sputtered tantalum atoms will deposit on the sidewall of the bottom via of the first dielectric layer; finally, forming a second tantalum metal layer, wherein in the bottom via of the first dielectric layer only exist the first tantalum metal layer and the second tantalum metal layer.

Abstract: A method for forming barrier layers comprises: first, forming a dual damascene structure on a metal layer of a wafer. The dual damascene structure includes a first dielectric layer and a second dielectric layer. There is a via in the first dielectric layer and there is a trench in the second dielectric layer; second, forming a first tantalum metal layer on the dual damascene structure; third, forming a tantalum nitride layer on the first tantalum metal layer, removing the tantalum nitride layer in the via bottom of the first dielectric layer with a ion-sputtering way and the sputtered tantalum atoms will deposit on the sidewall of the bottom via of the first dielectric layer; finally, forming a second tantalum metal layer, wherein in the bottom via of the first dielectric layer only exist the first tantalum metal layer and the second tantalum metal layer.

Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.