Patents by Inventor Yu Sheng

Yu Sheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240158309
    Abstract: The invention provides a material surface treatment equipment, which is applied to a material substrate. The material surface treatment equipment includes a surface treatment device and at least one waveguide device. The surface treatment device is used to carry the material substrate to perform a surface treatment process. Each waveguide device is used for introducing electromagnetic waves to the material substrate to assist in performing the surface treatment process. Through the introduction of electromagnetic waves, the surface treatment process of the material substrate is easy to perform and can achieve the strengthening effect.
    Type: Application
    Filed: December 15, 2022
    Publication date: May 16, 2024
    Inventors: TIEN-HSI LEE, JUN-HUANG WU, YU-SHENG CHIOU, SHU-CHENG LI, WEI-CHI HUANG, HSIN CHEN
  • Patent number: 11983351
    Abstract: A touch data transmission method of present disclosure includes: generating a header information by a first controller according to a detected touch event; generating a first checksum information by the first controller according to the header information; storing the header information and the first checksum information to a memory by the first controller; and, storing a plurality of position information of the detected touch event to the memory by the first controller.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: May 14, 2024
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chun-Kai Chuang, Jan-Ruei Lin, Yu-Hsiang Lin, I-Sheng Chao
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Patent number: 11982019
    Abstract: A crystal growth doping apparatus and a crystal growth doping method are provided. The crystal growth doping apparatus includes a crystal growth furnace and a doping device that includes a feeding tube inserted to the furnace body along an oblique insertion direction, and a storage cover and a gate tube that are disposed in the feeding tube. The feeding tube extends from an outer surface thereof to form a placement opening, and the placement opening is recessed from an edge thereof to form an upper recessed portion and a lower recessed portion along the oblique insertion direction. The storage cover includes a storage tank and a handle. When the storage cover is disposed in the gate tube body, the gate tube body is configured to isolate an inner space of the feeding tube from the placement opening.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 14, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Yu-Chih Chu, Tang-Chi Lin, Han-Sheng Wu, Hsien-Ta Tseng
  • Patent number: 11984378
    Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Chin-Hua Wang, Yu-Sheng Lin, Shin-Puu Jeng
  • Publication number: 20240153839
    Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen YEH, Po-Yao LIN, Chin-Hua WANG, Yu-Sheng LIN, Shin-Puu JENG
  • Publication number: 20240154215
    Abstract: An aluminum plastic film for a lithium battery and a method for manufacturing the same are provided. The method includes steps as follows: preparing a polyolefin adhesive; coating the polyolefin adhesive onto one surface of an aluminum foil layer; disposing an inner polyolefin layer onto the polyolefin adhesive; and drying the polyolefin adhesive, so that a polyolefin adhesive layer is formed between the aluminum foil layer and the inner polyolefin layer. Components of the polyolefin adhesive include a modified polyolefin polymer and a hardener. The modified polyolefin polymer has a modified group, a structure of the modified group contains maleic anhydride, and a molecular weight of the modified polyolefin polymer ranges from 100,000 g/mol to 200,000 g/mol.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 9, 2024
    Inventors: TE-CHAO LIAO, SHIOU-YEH SHENG, TENG-KO MA, CHING-YAO YUAN, Chao-Hsien Lin, CHIA-YU LIN, YUN-BIN HSI, HAN-YI LEE, SHUN-CHIEH YANG
  • Patent number: 11976018
    Abstract: Disclosed is a diamine compound represented by Formula (1), in which R1, R2, R3, R4, R5, X1, X2, X3, X4, m, n, a, b, c, and d are as defined herein. Also disclosed are a method for manufacturing the diamine compound, a composition including the diamine compound having a (chain alkoxy-methylene) phenyl group or a (hydroxyl-methylene) phenyl group, and a polymer including the (chain alkoxy-methylene) phenyl group or the (hydroxyl-methylene) phenyl group.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 7, 2024
    Assignee: DAXIN MATERIALS CORP.
    Inventors: Kai-Sheng Jeng, Yuan-Li Liao, You-Ming Chen, Yu-Ying Kuo, Shao-Chi Cheng
  • Patent number: 11978392
    Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 7, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Min-Yang Chiu, Yu-Sheng Ma, Jin-Yi Lin, Hsuan-Yu Chen, Jhih-Siou Cheng, Chun-Fu Lin
  • Publication number: 20240139990
    Abstract: An internal rotor type nail drive device of electric nail gun, comprising a nailing rod and an internal rotor type rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator comprises a stator and a rotor arranged inside the stator, even groups of electromagnetic mutual action components are configured in pairs between the stator and the rotor, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by a specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified, and the kinetic energy for nailing can be increased.
    Type: Application
    Filed: August 22, 2023
    Publication date: May 2, 2024
    Inventors: I-TSUNG WU, CHIA-SHENG LIANG, YU-CHE LIN, WEN-CHIN CHEN
  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Publication number: 20240144999
    Abstract: A memory circuit and a method for reading a memory circuit are provided. The memory circuit includes reference memory cells and operation memory cells. The method includes reading a selected reference memory cell at a first time to get a first voltage; reading the selected reference memory cell at a second time after the first time to get a second voltage; adjusting a read voltage of the memory cell to be an adjusted read voltage of the memory cell according to the voltage difference between the first voltage and the second voltage; applying the adjusted read voltage on a selected operation memory cell corresponding to the selected reference memory cell; and applying the adjusted read voltage on other selected operation memory cells in a same row of the memory array corresponding to the selected reference memory cell.
    Type: Application
    Filed: February 2, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Yu-Sheng Chen, Xinyu BAO
  • Publication number: 20240145342
    Abstract: In an embodiment, a package includes an encapsulant laterally surrounding a first integrated circuit device and a second integrated circuit device, wherein the first integrated circuit device includes a die and a heat dissipation structure over the die; a sealant disposed over the heat dissipation structure; an adhesive disposed over the second integrated circuit device; and a lid disposed over the sealant and the adhesive, wherein the lid includes a first cooling passage and a second cooling passage, the first cooling passage including an opening at a bottom of the lid and aligned to the heat dissipation structure, the second cooling passage including channels aligned to the second integrated circuit device and being distant from the bottom of the lid.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 2, 2024
    Inventors: Tung-Liang Shao, You-Rong Shaw, Yu-Sheng Huang, Chen-Hua Yu
  • Publication number: 20240142400
    Abstract: A bioelectronic system for rare cell separation and an application thereof. The bioelectronic system comprises: an electrode; a conductive polymer layer located on a surface of the electrode; a conductive polymer fiber layer located on the surface of the conductive polymer layer not in contact with the electrode; and a rare cell capturing material located the surface of the conductive polymer fiber layer not in contact with the conductive polymer layer. The conductive polymer layer has a thickness of 10-2000 nanometers. A method for rare cell separation can be provided using the bioelectronic system, and includes: introducing a biological fluid containing a rare cell into the bioelectronic system to capture the rare cell; and providing an electrical stimulus by using the electrode of the bioelectronic system to release the captured rare cell.
    Type: Application
    Filed: March 2, 2022
    Publication date: May 2, 2024
    Inventors: Yu-Sheng HSIAO, Shih-Ming TSAI
  • Publication number: 20240142961
    Abstract: A method of estimating greenhouse gas emission, performed by a processing device, includes: obtaining at least one time period of a number of working stations for a target manufacturing process of a product; obtaining a number of first power consumption data of the target manufacturing process, wherein the first power consumption data correspond to the working stations respectively; calculating a number of second power consumption data based on the at least one time period and the first power consumption data; searching for a number of target coefficients corresponding to the plurality of working stations respectively in coefficient database based on the target manufacturing process; and calculating greenhouse gas emission data of the target manufacturing process based on the second power consumption data and the target coefficients.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Tsung-Hsi LIN, Yun Sheng LI, Yu Ling LEE, Hsiao Pin LIN, Chia Hou CHEN
  • Patent number: 11972786
    Abstract: Provided are a function switchable random access memory, including: two electromagnetic portions configured to connect a current; a magnetic recording portion between the two electromagnetic portions and including a spin-orbit coupling layer and a magnetic tunnel junction; a pinning region between each of the electromagnetic portions and the magnetic recording portion; a cut-off region on a side of each of the electromagnetic portions opposite to the pinning region, the spin-orbit coupling layer is configured to generate a spin current under an action of the current; the two electromagnetic portions is configured to generate two magnetic domains with magnetization pointing in opposite directions under an action of the spin current; the magnetic tunnel junction is configured to generate a magnetic domain wall based on the two opposite magnetic domains and is configured to drive the magnetic domain wall to reciprocate under the action of the spin current.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: April 30, 2024
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Kaiyou Wang, Yu Sheng
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Patent number: D1024959
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 30, 2024
    Assignee: VOLTRONIC POWER TECHNOLOGY CORP.
    Inventors: You-Sheng Chiang, Yu-Cheng Lu, Juor-Ming Hsieh
  • Patent number: D1026816
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 14, 2024
    Assignee: VOLTRONIC POWER TECHNOLOGY CORP.
    Inventors: You-Sheng Chiang, Yu-Cheng Lu, Juor-Ming Hsieh
  • Patent number: D1026817
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 14, 2024
    Assignee: VOLTRONIC POWER TECHNOLOGY CORP.
    Inventors: You-Sheng Chiang, Yu-Cheng Lu, Juor-Ming Hsieh