Patents by Inventor Yu-Sheng Chen

Yu-Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11078593
    Abstract: A radiative cooling substrate and a manufacturing method of the radiative cooling substrate are provided. The radiative cooling substrate includes a metallic substrate and a chitosan layer disposed on the metallic substrate with a thickness of 0.5 ?m to 10 ?m. The chitosan layer emits radiation within a waveband between 8 ?m and 13 ?m.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 3, 2021
    Assignee: National Tsing Hua University
    Inventors: Yu-Bin Chen, Hung-Sheng Han
  • Publication number: 20210217622
    Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.
    Type: Application
    Filed: June 9, 2020
    Publication date: July 15, 2021
    Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
  • Publication number: 20210210137
    Abstract: A method of operating a synapse array includes applying a pulse sequence to a resistor coupled between a row and a column of the synapse array, and in response to the applying the pulse sequence, lowering a conductance level of the resistor. Each pulse of the pulse sequence includes a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and applying the pulse sequence includes increasing the pulse number while increasing one of the amplitude, the pulse width, or the trailing edge duration.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Yu-Sheng CHEN, Jau-Yi WU, Chia-Wen CHANG
  • Patent number: 11042254
    Abstract: A touch display device includes a substrate. The substrate includes a display area, a non-display area, a first touch area, and a non-touch area. A first touch grid is disposed within the first touch area. A second touch grid is electrically isolated from the first touch grid and disposed within the first touch area. A first wire is disposed within the non-touch area and electrically connected to the first touch grid. A second wire is disposed within the non-touch area and electrically connected to the second touch grid. The first wire and the second wire are staggered and are electrically isolated from each other. The second wire includes at least two separate conductive units and at least one bridge wire connected to the at least two separate conductive units. An insulating layer is disposed between the first wire and the second wire.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 22, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Hao-Yu Liou, Hong-Sheng Hsieh, Yu-Sheng Chen, Jian-Cheng Chen, Ying-Shiang Huang, Chin-Lung Ting, Chung-Kuang Wei
  • Patent number: 10998660
    Abstract: A connector assembly includes a first electronic component, an electrical connector and a shielding shell fixed to the first electronic component, a second electronic component located above the first electronic component, and a mating member fixed to the second electronic component. The electrical connector includes an insulating body, and a first terminal electrically connected to the first electronic component. The mating member includes a second terminal electrically connected to the second electronic component. The shielding shell has a first grounding portion and a second grounding portion, and covers outside the first terminal. The first grounding portion is electrically connected to the first electronic component.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 4, 2021
    Assignee: LOTES CO., LTD
    Inventor: Yu Sheng Chen
  • Patent number: 10971223
    Abstract: A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Sheng Chen, Jau-Yi Wu, Chia-Wen Chang
  • Publication number: 20210088818
    Abstract: A display device is provided. The display device includes a display having a display area. The display includes a first substrate and an antistatic layer. The first substrate has a first side and a second side, the second side is opposite to the first side. The antistatic layer is disposed on the first side and has a plurality of hollow areas. At least a portion of the antistatic layer overlaps the display area in a normal direction of the first substrate.
    Type: Application
    Filed: August 24, 2020
    Publication date: March 25, 2021
    Inventors: Hong-Sheng HSIEH, Yu-Sheng CHEN, Bo-Hao SONG
  • Publication number: 20210083181
    Abstract: A memory device includes a conductive wire, a first 2-D material layer, a phase change element, and a top electrode. The first 2-D material layer is over the conductive wire. The phase change element extends along a surface of the first 2-D material layer distal to the conductive layer. The top electrode is over the phase change element.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng CHEN, Da-Ching CHIOU, Jau-Yi WU, Carlos H. DIAZ
  • Publication number: 20210065792
    Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jau-Yi WU, Win-San KHWA, Jin CAI, Yu-Sheng CHEN
  • Publication number: 20210066590
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.
    Type: Application
    Filed: October 27, 2020
    Publication date: March 4, 2021
    Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
  • Publication number: 20210043254
    Abstract: A method, includes: applying a read voltage at a first read voltage level to read a memory cell for detecting a resistance level of the memory cell; applying the read voltage at a second read voltage level, different from the first read voltage level, to read the memory cell for determining a waveform type has been utilized to program the memory cell; recognizing data bits stored in the memory cell. The data bits stored in the memory cell comprise a first data bit and at least one second data bit. The first data bit is recognized according to the waveform type and is irrelevant with the resistance level. The at least one second data bit is recognized according to the resistance level and is irrelevant with the waveform type. A device is also disclosed herein.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jau-Yi Wu, Yu-Sheng Chen
  • Publication number: 20210035633
    Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
    Type: Application
    Filed: March 2, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Sheng Chen, Hon-Sum Philip Wong
  • Publication number: 20210024166
    Abstract: A coupling mechanism for a vehicle body having mutually pivotable first and second frames comprises an axle fixed to the first frame, a rotating member fixed to the second frame and rotatably mounted around the axle, and a torsional resistance module that is actuated when the axle and the rotating member rotate relative to each other. The torsional resistance module includes two force magnifying mechanisms connected between the first frame and the rotating member. A buffering member is disposed between the force magnifying mechanisms. When the buffering member is pressed, a relative torsional resistance is provided between the first and second frames through transmission of the force magnifying mechanisms. The torsional resistance has a non-linear relationship with a relative rotational angle between the first and second frames.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 28, 2021
    Inventors: CHYUAN-YOW TSENG, KENG-YU KO, YU-SHENG CHEN
  • Patent number: 10862031
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
  • Patent number: 10847221
    Abstract: A method is disclosed including following operations. A first signal is applied to memory cells in a memory device, to adjust resistance values of the memory cells. After the first signal is applied, a second signal is applied to the memory cells other than the first memory cell, to further adjust the resistance values of the plurality of memory cells other than the first memory cell. After the second signal is applied, data corresponding to the first predetermined resistance value and the second predetermined resistance value is stored in the first memory cell and the second memory cell, respectively. The first signal is configured for controlling a first memory cell in the memory cells to have a first predetermined resistance value. The second signal is configured for controlling a second memory cell in the memory cells to have a second predetermined resistance value.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jau-Yi Wu, Win-San Khwa, Jin Cai, Yu-Sheng Chen
  • Publication number: 20200343446
    Abstract: Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Sheng Chen
  • Patent number: 10818349
    Abstract: Methods for programming or reading a memory cell are disclosed. The methods include following operations. A read voltage at a first read voltage level is applied to read a memory cell for detecting a resistance level of the memory cell. The read voltage at a second read voltage level, different from the first read voltage level, is applied to read the memory cell for determining a waveform type has been utilized to program the memory cell. The resistance level and the waveform type are combined to recognize data bits stored in the memory cell.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jau-Yi Wu, Yu-Sheng Chen
  • Patent number: 10804008
    Abstract: An electrical component includes an insulating base, an insulating layer provided outside the insulating base, a shielding member provided between the insulating base and the insulating layer, and multiple conductive bodies accommodated in the insulating base. The conductive bodies include at least one power supply body. Each of the at least one power supply body is provided with a shielding layer outside the power supply body and an insulator between the power supply body and the shielding layer. The shielding layer is accommodated in the shielding member. In the electrical component, by providing a shielding layer and an insulator provided between the power supply body and the shielding layer outside the power supply body, shielding of the shielding layer from the power supply body is implemented, so as to reduce an interference of the power supply body on a signal body, thereby improving transmission quality of high-frequency signals.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: October 13, 2020
    Assignee: LOTES CO., LTD
    Inventors: Chin Chi Lin, Yu Sheng Chen
  • Publication number: 20200295489
    Abstract: A connector assembly includes a first electronic component, an electrical connector and a shielding shell fixed to the first electronic component, a second electronic component located above the first electronic component, and a mating member fixed to the second electronic component. The electrical connector includes an insulating body, and a first terminal electrically connected to the first electronic component. The mating member includes a second terminal electrically connected to the second electronic component. The shielding shell has a first grounding portion and a second grounding portion, and covers outside the first terminal. The first grounding portion is electrically connected to the first electronic component.
    Type: Application
    Filed: January 30, 2020
    Publication date: September 17, 2020
    Inventor: Yu Sheng Chen
  • Publication number: 20200290248
    Abstract: A method for manufacturing a formed member is provided. A metal sheet is provided in a mold including a mold cavity. An upper end as well as each of left and right sides of the mold cavity are in communication with at least one first upper runner channel and at least one side runner channel. A liquid insulating material is injected into the mold and flows into the mold cavity from the first upper runner channel and the side runner channel respectively. After the liquid insulating material is solidified, a body is formed in the mold cavity, a first upper connecting portion is formed in each first upper runner channel, and a side connecting portion is formed in each side runner channel. Then the formed member is obtained by disconnecting the joints of the body and each of the first upper connecting portion as well as the side connecting portion.
    Type: Application
    Filed: December 18, 2019
    Publication date: September 17, 2020
    Inventors: Chin Chi Lin, Yu Sheng Chen