Patents by Inventor Yu-Sheng Hsieh

Yu-Sheng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879170
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.
    Type: Grant
    Filed: April 21, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chung-Shi Liu, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Chang-Wen Huang, Yu-Sheng Hsieh, Ching-Yu Huang
  • Publication number: 20200335439
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.
    Type: Application
    Filed: April 21, 2019
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chung-Shi Liu, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Chang-Wen Huang, Yu-Sheng Hsieh, Ching-Yu Huang
  • Publication number: 20200258799
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 10636713
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20200075526
    Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20200020628
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 10504865
    Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 10345147
    Abstract: An optical package is provided. The optical package includes an interference splitter allowing a light having a predetermined wavelength range to transmit through, a sensing element, and a light-transmitting structure. The light-transmitting structure includes a light-transmitting pillar and a light-absorbing layer surrounding the light-transmitting pillar, and the light-absorbing layer absorbs the light having the predetermined wavelength range. The interference splitter, the light-transmitting pillar, and the sensing element are arranged aligned with each other along an extending direction of the light-transmitting pillar. The sensing element is configured to receive the light transmitting through the interference splitter and the light-transmitting pillar.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 9, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Jung Chang, Yu-Sheng Hsieh, Jing-Yuan Lin, Chih-Hao Hsu
  • Publication number: 20190115271
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 18, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20190096841
    Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 10183858
    Abstract: The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Albert Wan, Yu-Sheng Hsieh, Chao-Wen Shih, Shou Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10157807
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20180148317
    Abstract: The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Application
    Filed: March 10, 2017
    Publication date: May 31, 2018
    Inventors: ALBERT WAN, YU-SHENG HSIEH, CHAO-WEN SHIH, SHOU ZEN CHANG, CHUNG-SHI LIU, CHEN-HUA YU
  • Publication number: 20180087962
    Abstract: An optical package is provided. The optical package includes an interference splitter allowing a light having a predetermined wavelength range to transmit through, a sensing element, and a light-transmitting structure. The light-transmitting structure includes a light-transmitting pillar and a light-absorbing layer surrounding the light-transmitting pillar, and the light-absorbing layer absorbs the light having the predetermined wavelength range. The interference splitter, the light-transmitting pillar, and the sensing element are arranged aligned with each other along an extending direction of the light-transmitting pillar. The sensing element is configured to receive the light transmitting through the interference splitter and the light-transmitting pillar.
    Type: Application
    Filed: December 27, 2016
    Publication date: March 29, 2018
    Inventors: Chia-Jung CHANG, Yu-Sheng HSIEH, Jing-Yuan LIN, Chih-Hao HSU
  • Publication number: 20170345731
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: August 12, 2016
    Publication date: November 30, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20170139200
    Abstract: A tunable optical device including a substrate, at least one support unit, a flexible frame, an elastic component, a first reflector, and at least one actuator is provided. The support unit is fixed onto the substrate. The flexible frame is connected to the support unit and suspended above the substrate. The elastic component is connected to the flexible frame. A stiffness of the elastic component in the Z-axis is smaller than a stiffness of the flexible frame in the Z-axis. The Z-axis direction is parallel to a normal direction of the substrate. The first reflector is connected to the elastic component. The actuator is located between the flexible frame and the substrate or located between the first reflector and the substrate.
    Type: Application
    Filed: March 11, 2016
    Publication date: May 18, 2017
    Inventors: Chia-Jung Chang, Jing-Yuan Lin, Chun-Kai Mao, Jien-Ming Chen, Yu-Sheng Hsieh
  • Patent number: 9400224
    Abstract: A pressure sensor and a manufacturing method of the same are provided. The pressure sensor includes a substrate, a dielectric oxide layer, a first electrode, a dielectric connection layer, and a second electrode. The dielectric oxide layer is formed on the substrate. The first electrode is formed on the dielectric oxide layer. The dielectric connection layer is formed on the first electrode. The second electrode is formed on the dielectric connection layer. The second electrode comprises a patterned conductive layer and a dielectric layer. The patterned conductive layer has a plurality of holes, and the dielectric layer is formed on the patterned conductive layer and covers the inner walls of the plurality of holes. The first electrode, the dielectric connection layer, and the second electrode define a first chamber between the first electrode and the second electrode.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 26, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Jien-Ming Chen, Chin-Wen Huang, Chin-Hung Wang, Jing-Yuan Lin, Yu-Sheng Hsieh
  • Publication number: 20160076959
    Abstract: A pressure sensor and a manufacturing method of the same are provided. The pressure sensor includes a substrate, a dielectric oxide layer, a first electrode, a dielectric connection layer, and a second electrode. The dielectric oxide layer is formed on the substrate. The first electrode is formed on the dielectric oxide layer. The dielectric connection layer is formed on the first electrode. The second electrode is formed on the dielectric connection layer. The second electrode comprises a patterned conductive layer and a dielectric layer. The patterned conductive layer has a plurality of holes, and the dielectric layer is formed on the patterned conductive layer and covers the inner walls of the plurality of holes. The first electrode, the dielectric connection layer, and the second electrode define a first chamber between the first electrode and the second electrode.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Jien-Ming Chen, Chin-Wen Huang, Chin-Hung Wang, Jing-Yuan Lin, Yu-Sheng Hsieh
  • Patent number: 8859317
    Abstract: A gas sensor manufacturing method comprises the following steps: providing a SOI substrate, including an oxide layer, a device layer, and a carrier, wherein the oxide layer is disposed between the device layer and the carrier; etching the device layer to form an integrated circuit region, an outer region, a trench and at least one conducting line; coating or imprinted a sensing material on the integrated circuit region; and etching the carrier and the oxide layer to form a cavity up to the gap so as to form a film structure which is suspended in the cavity by the cantilevered connecting arm.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 14, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yu Sheng Hsieh, Jing Yuan Lin, Shang Chian Su
  • Patent number: 8693711
    Abstract: A capacitive transducer and fabrication method are disclosed. The capacitive transducer includes a substrate, a first electrode mounted on the substrate, a cap having a through-hole and a cavity beside the through-hole, a second electrode mounted on the cap across the through-hole. The second electrode is deformable in response to pressure fluctuations applied thereto via the through-hole and defines, together with the first electrode, as a capacitor. The capacitor includes a capacitance variable with the pressure fluctuations and the cavity defines a back chamber for the deformable second electrode.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: April 8, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Tzong-Che Ho, Lung-Tai Chen, Yao-Jung Lee, Chao-Ta Huang, Li-Chi Pan, Yu-Sheng Hsieh