Patents by Inventor Yu-Sheng Lin

Yu-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367311
    Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen YEH, Po-Yao LIN, Chin-Hua WANG, Yu-Sheng LIN, Shin-Puu JENG
  • Patent number: 11499219
    Abstract: A method of fabricating a thin film with a varying thickness includes the steps of providing a shadow mask with an opening, providing a carrier plate, arranging a substrate on the carrier plate, and coating the substrate through the opening whilst rotating the carrier plate relative to the shadow mask. A plurality of zones of the substrates is swept and exposed from arcuate portions of the opening per each turn by a plurality of predetermined exposure times, respectively. The varying thickness of the thin film corresponds to variation of the predetermined exposure times.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 15, 2022
    Assignee: National Chiao Tung University
    Inventors: Cheng-Sheng Huang, Chi-Yung Hsieh, Yu-Chi Lin, Chih-Chung Wu, Chi-Fang Huang
  • Publication number: 20220359431
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20220359465
    Abstract: A package structure is provided. The package structure includes a first package component, a second package component, and a lid structure. The first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. The second package component includes a substrate, and the first package component is mounted on the substrate. The lid structure is disposed on the second package component and around the first package component, and the lid structure covers the integrated circuit dies and exposes the underfill.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua WANG, Shu-Shen YEH, Yu-Sheng LIN, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20220359425
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
  • Patent number: 11495155
    Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: November 8, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Chin-Hsien Tseng, Po-Cheng Lai, Yu-Sheng Lin, Mao-Hsun Cheng
  • Publication number: 20220349097
    Abstract: The invention provides a circular knitting machine for prompting a knitting machine status instantaneously based on a cloth surface status of a fabric, comprising a needle cylinder, a camera module capable of photographing the fabric during doffing, an information processing unit, and an encoder. A camera lens of the camera module does not rotate with the needle cylinder, and a shooting timing of the camera lens is controlled by photographing signals. The information processing unit receives image data generated by the camera module, and compares the images, when there is a difference between the two consecutive image data on a same vertical line, a knitting machine status is prompted. The encoder generates pulse signals when the needle cylinder rotates, the encoder outputs the pulse signals to the camera module or the information processing unit, and the receiver counts the pulse signals to generate the photographing signals.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Yu-Sheng LIN, Hsien-Te TSAI
  • Patent number: 11489657
    Abstract: Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 1, 2022
    Assignee: Diodes Incorporated
    Inventors: Yu-Wei Lin, Yi Sheng Lin, Nanyuan Chen
  • Publication number: 20220344582
    Abstract: A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Yu-Sheng Chen, Carlos H. Diaz, Da-Ching Chiou
  • Publication number: 20220344583
    Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.
    Type: Application
    Filed: July 20, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Yu-Sheng Chen, Da-Ching Chiou
  • Publication number: 20220334880
    Abstract: A tensor accelerator includes two tile execution units and a bidirectional queue. Each of the tile execution units includes a buffer, a plurality of arithmetic logic units, a network, and a selector. The buffer includes a plurality of memory cells. The network is coupled to the plurality of memory cells. The selector is coupled to the network and the plurality of arithmetic logic units. The bidirectional queue is coupled between the selectors of the tile execution units.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Shao-Yi Chien, Yu-Sheng Lin, Wei-Chao Chen
  • Publication number: 20220336318
    Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Inventors: Yu-Sheng LIN, Po-Yao LIN, Shu-Shen YEH, Chin-Hua WANG, Shin-Puu JENG
  • Publication number: 20220336537
    Abstract: An OLED touch and display driver integration chip is provided, including: a group of display driving pads for providing display driving signals to the OLED touch display panel; a group of touch pads for providing touch driving signals to touch electrodes on the OLED touch display panel and/or receiving touch sensing signals from the touch electrodes, and adjacently arranged with the group of display driving pads; and at least one isolation pad arranged between the group of display driving pads and the group of touch pads.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Chang-Hung Chen, Kun-Zheng Lin, Wei-Chieh Lin, Po-Sheng Liao, Yu-Huang Chen
  • Patent number: 11467268
    Abstract: Disclosures of the present invention describe an optical proximity sensor, which is particularly designed to have functionality of canceling an ambient light noise and/or an optical crosstalk noise by using light-to-frequency conversion technique, and comprises: a controlling and processing circuit, a lighting unit, a light receiving unit, an analog adder, a first DAC unit, a second DAC unit, and a light-to-digital conversion (LDC) unit. In the controlling of the controlling and processing circuit, the first DAC unit and the second DAC unit would respectively generate a first compensation current signal and a second compensation current signal to the analog adder, such that a noise signal of ambient light and a noise signal of optical crosstalk existing in an optical current signal of object reflection light would be canceled by the two compensation current signals in the analog adder.
    Type: Grant
    Filed: June 23, 2019
    Date of Patent: October 11, 2022
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corporation
    Inventors: Wen-Sheng Lin, Sheng-Cheng Lee, Yu-Cheng Su, Peng-Han Chan, Chun-Hsien Lin
  • Publication number: 20220310502
    Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Chen, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20220310501
    Abstract: A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20220310474
    Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Application
    Filed: June 29, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Publication number: 20220302011
    Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.
    Type: Application
    Filed: July 15, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
  • Publication number: 20220301971
    Abstract: A package structure includes a circuit substrate, a semiconductor package, a thermal interface material, a lid structure and a heat dissipation structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The thermal interface material is disposed on the semiconductor package. The lid structure is disposed on the circuit substrate and surrounding the semiconductor package, wherein the lid structure comprises a supporting part that is partially covering and in physical contact with the thermal interface material. The heat dissipation structure is disposed on the lid structure and in physical contact with the supporting part of the lid structure.
    Type: Application
    Filed: July 4, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Po-Yao Lin, Shu-Shen Yeh, Chin-Hua Wang, Shin-Puu Jeng
  • Patent number: 11450480
    Abstract: The present disclosure provides a transformer module and a power module, wherein the transformer module comprises: a magnetic core, a first metal winding and a second metal winding. A first wiring layer, a first insulating layer and a second wiring layer are sequentially disposed on the magnetic core from the outside to the inside; the first metal winding is formed on the first wiring layer and winded around the magnetic core in a foil structure; the first insulating layer is at least partially covered by the first metal winding; a second metal winding is formed on the second wiring layer and winded around the magnetic core in a foil structure, wherein the second metal winding is at least partially covered by the first insulating layer, and is at least partially covered by the first metal winding.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 20, 2022
    Assignee: Delta Electronics (Shanghai) Co., Ltd.
    Inventors: Chaofeng Cai, Xiaoni Xin, Jianhong Zeng, Shouyu Hong, Rui Wu, Haoyi Ye, Yiqing Ye, Jinping Zhou, Zhiheng Fu, Min Zhou, Yu-Ching Kuo, Tong-Sheng Pan, Wen-Yu Lin