Abstract: A semiconductor die package is provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.

Abstract: A booster engine enhances the quality of a frame sequence. The booster engine receives, from a first stage circuit, the frame sequence with quality degradation in at least a frame. The the quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine queries an information repository for reference information on the frame, using a query input based on at least a region of the frame to obtain a query output. The booster engine then applies a neural network to the query input and the query output to generate an optimized frame, and sends an enhanced frame sequence including the optimized frame to a second stage circuit.

Abstract: Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a reinforcing structure over the circuit substrate. The reinforcing structure partially surrounds a corner of the die package. The package structure further includes an underfill structure surrounding the bonding structure. The underfill structure is in direct contact with the reinforcing structure.

Abstract: The quality of a frame sequence is enhanced by a booster engine collaborating with a first stage circuit. The first stage circuit adjusts the quality degradation of the frame sequence when a condition in constrained resources is detected. The quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine receives the frame sequence from the first stage circuit, and generates an enhanced frame sequence based on the frame sequence for transmission to a second stage circuit.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.

Abstract: A semiconductor package includes a substrate, a first semiconductor device disposed over the substrate in an offset position toward an edge of the substrate, and a ring structure disposed over the substrate and surrounding the first semiconductor device. The ring structure includes an overhang portion cantilevered over the edge of the substrate.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a warpage-control element attached to the circuit substrate. The warpage-control element has a protruding portion extending into the circuit substrate. The warpage-control element has height larger than that of the die package.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, two semiconductor dies over the interposer substrate, and an underfill element formed over the interposer substrate and surrounding the semiconductor dies. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. Recessed parts are recessed from the bottom surface of the ring structure. The recessed parts include multiple first recessed parts arranged in each corner area of the ring structure and two second recessed parts arranged in opposite side areas of the ring structure and aligned with a portion of the underfill element between the semiconductor dies. An adhesive layer is interposed between the bottom surface of the ring structure and the package substrate.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first tier, a second tier, and a third tier. The first tier includes an interposer. The second tier is disposed on the first tier and includes a bottom die. The third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. The at least one second die is disposed between the plurality of first dies. The plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.

Abstract: In an embodiment, a three-dimensional integrated circuit (3DIC) package includes an interposer, a plurality of connection pads, a plurality of dummy patterns, a plurality of integrated circuit structures and an underfill layer. The connection pads are disposed on and electrically connected to a first side of the interposer. The dummy patterns are disposed on the first side of the interposer and around the plurality of connection pads. The integrated circuit structures are electrically connected to the connection pads through a plurality of first bumps. The underfill layer surrounds the first bumps and covers the dummy patterns.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a recess in a circuit substrate, and the recess has a first sidewall and a second sidewall. The second sidewall is between the first sidewall and a bottommost surface of the circuit substrate, and the second sidewall is steeper than the first sidewall. The method also includes forming a die package, and the die package has a semiconductor die. The method further includes bonding the die package to the circuit substrate through bonding structures such that a portion of the semiconductor die enters the recess of the circuit substrate. In addition, the method includes forming an underfill material to surround the bonding structures and to fill the recess.

Abstract: A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.

Abstract: Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.

Abstract: A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.

Abstract: A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.

Abstract: A sensing device is provided. The sensing device includes a plurality of infrared thermosensitive elements and a plurality of resistor-capacitor (RC) oscillators. The plurality of infrared thermosensitive elements are arranged in an array. Each of the plurality of infrared thermosensitive elements has a resistance value which changes with a temperature of the infrared thermosensitive element by absorbing infrared radiation and generates a sensing voltage corresponding to the resistance value. The plurality of RC oscillators are coupled to the plurality of infrared thermosensitive elements to receive the corresponding sensing values, respectively. Each of the plurality of RC oscillators generates a digital sensing signal according to the corresponding sensing value to indicate the temperature of the corresponding infrared thermosensitive element. Each of the plurality of RC oscillators is disposed under the corresponding infrared thermosensitive element.

Abstract: Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.