Patents by Inventor Yu-Shiang Lin
Yu-Shiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210176329Abstract: A control method of a system supporting fault tolerance is provided, at first, a first host executes a transmission control protocol agent to receive a data stream from a client device. Then the TCP agent transmits an acknowledgement packet to the client device in response to the data stream from the client device. Then the TCP agent determines whether a fault tolerance mechanism of the virtual machine is activated. When the TCP agent determines that the fault tolerance mechanism of the virtual machine is activated, the TCP agent determines whether the virtual machine operates in a running state. When the TCP agent determines that the virtual machine is not in the running state, the TCP agent temporarily storing the data stream. When the TCP agent determines that the virtual machine operates in a running state, the TCP agent transmits the data stream to the virtual machine.Type: ApplicationFiled: July 28, 2020Publication date: June 10, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Kai LIN, Po-Jui TSAO, Yu-Shiang LIN
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Patent number: 10083880Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: GrantFiled: April 24, 2017Date of Patent: September 25, 2018Assignee: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Publication number: 20170229353Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Patent number: 9715437Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.Type: GrantFiled: January 22, 2016Date of Patent: July 25, 2017Assignee: International Business Machines CorporationInventors: Jae-Joon Kim, Yu-Shiang Lin, Insup Shin
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Patent number: 9653615Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: GrantFiled: March 13, 2013Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Publication number: 20160228882Abstract: A negative ionizer air purifier is provided. It includes a power adapter, a high-voltage generator and discharge terminals. A first input terminal of the power adapter connects to the live wire of the AC mains, a second input terminal connects to the naught wire, and the third input terminal connects to the earth wire. The power adapter converts an AC voltage inputted through its first and second input terminals to a low DC voltage and outputs it to the high-voltage generator, which further boosts the low DC voltage to a high DC voltage and outputs it. The first output terminal of the high-voltage generator connects to the discharge terminals, and the second output terminal connects to a reference earth and also to the third input terminal of the power adapter, where the reference earth refers to the housing of the negative air purifier.Type: ApplicationFiled: November 12, 2013Publication date: August 11, 2016Applicant: Shenzhen China Star Optoelectronics Technology Co. , Ltd.Inventors: Yu-shiang LIN, Fujun SUN
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Publication number: 20160221002Abstract: A negative ionizer air purifier is disclosed and it includes a housing, discharge terminals and a fan. The housing is defined with receiving holes corresponding to the discharge terminals, which are disposed through the respective receiving holes. The fan is disposed inside the housing, on which is provided with airflow passages through which the airflow produced by the fan can drive the air near the discharge terminals to move. Thus, the speed of the airflow surrounding near the discharge terminals can be accelerated, such that more air which is not negatively charged can fill in the working area in the vicinity of the discharge terminals, and the air that is already negatively charged can be driven away as quickly as possible, hence the efficiency of the negative ionizer air purifier can be significantly improved.Type: ApplicationFiled: November 12, 2015Publication date: August 4, 2016Applicant: Shenzhen China Star Optoelectronics Technology Co. , Ltd.Inventors: Yu-shiang LIN, Fujun SUN
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Publication number: 20160140005Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.Type: ApplicationFiled: January 22, 2016Publication date: May 19, 2016Inventors: Jae-Joon Kim, Yu-Shiang Lin, Insup Shin
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Patent number: 9292390Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.Type: GrantFiled: July 15, 2013Date of Patent: March 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jae-Joon Kim, Yu-Shiang Lin, Insup Shin
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Patent number: 9087909Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: GrantFiled: August 7, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Patent number: 9009545Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.Type: GrantFiled: June 14, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Jae-Joon Kim, Yu-Shiang Lin, Insup Shin
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Publication number: 20140372827Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Jae-Joon Kim, Yu-Shiang Lin, Insup Shin
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Publication number: 20140372797Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.Type: ApplicationFiled: July 15, 2013Publication date: December 18, 2014Inventors: Jae-Joon Kim, Yu-Shiang Lin, Insup Shin
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Publication number: 20140264593Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporaitonInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Publication number: 20140264605Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: ApplicationFiled: August 7, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Patent number: 8587357Abstract: There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.Type: GrantFiled: August 25, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Jae-Joon Kim, Yu-Shiang Lin, Liang-Teck Pang, Joel A. Silberman
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Patent number: 8576000Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.Type: GrantFiled: August 25, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Jae-Joon Kim, Yu-Shiang Lin, Liang-Teck Pang, Joel A. Silberman
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Patent number: 8466739Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.Type: GrantFiled: September 7, 2012Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Jae-Joon Kim, Yu-Shiang Lin, Liang-Teck Pang, Joel A. Silberman
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Publication number: 20130049828Abstract: There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JAE-JOON KIM, YU-SHIANG LIN, LIANG-TECK PANG, JOEL A. SILBERMAN
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Publication number: 20130049826Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.Type: ApplicationFiled: September 7, 2012Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JAE-JOON KIM, YU-SHIANG LIN, LIANG-TECK PANG, JOEL A. SILBERMAN