Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

Abstract: A network power supply control system is applicable to a network power supply equipment (PSE) and a network power device (PD) connected through a network cable. A signal generator is disposed on the network PSE for generating and combining an operating signal with a power signal provided by the network PSE. A signal analyzer is disposed on the network PD for extracting the operating signal from the power signal received by the network PD and controlling a load circuit of the network PD according to the operating signal. Alternatively, the signal generator is disposed on the PD and sends a operating signal according to a state of the load circuit and combines the operating signal with a return power signal returned by the network PD, and the signal analyzer is disposed on the PSE for extracting the operating signal from the return power signal received by the network PSE.

Abstract: A method of forming damascene structures. A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. A gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photoresist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photoresist pattern to form a plurality of trenches.

Abstract: A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. A gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photoresist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photoresist pattern to form a plurality of trenches.