Abstract: A touch panel includes a substrate, scan lines, data lines, sub-pixels, a first conductive line, a second conductive line, and a conductive layer. The sub-pixels are arranged in columns along a first direction and arranged in rows along a second direction. Each of the sub-pixels includes an active element and a pixel electrode electrically connected with the active element. The active element is electrically connected with a corresponding scan line and a corresponding data line. The conductive layer overlaps the sub-pixels. The conductive layer includes a first electrode and a second electrode. The first electrode is electrically connected with the first conductive line. The second electrode is electrically connected with the second conductive line. The second electrode is separated from the first electrode. One of the first electrode and the second electrode is a touch electrode, and another one is a common electrode.

Abstract: A method for enhancing network coverage based on adaptive generation of resource cell. A traditional cell in a network is taken as an initial state of the network. A correlation matrix in a current network state is generated. Whether |?i,jt??i,jt-1|/?i,jt-1>? is determined. Each access point is divided into a plurality of resource cells. A CU-DU network mapping table is generated. A middlehaul link of each of the plurality of resource cells is constructed according to the CU-DU network mapping table.

Abstract: An image processing circuit is configured to generate a first offset value according to second offset values in at least one look-up table corresponding to a starting voltage range of at least one illumination element in a display device. The image processing circuit is further configured to generate output image data according to an ending gray level value and the first offset value. The output image data is for overdriving the at least one illumination element. The second offset values correspond to a starting gray level value of a first frame and the ending gray level value of a second frame.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: An electronic device according to an embodiment of the disclosure may include a loop antenna, a printed circuit board including a power wire and a ground wire, a first switch electrically connected between a first terminal of the loop antenna and the power wire, a second switch electrically connected between the first terminal and the ground wire, a third switch electrically connected between a second terminal of the loop antenna and the power wire, a fourth switch electrically connected between the second terminal and the ground wire, and a controller.

Abstract: A method for detecting people entering and leaving a field is provided in an embodiment of the disclosure. The method includes the following. An event detection area corresponding to an entrance is set, and the event detection area includes an upper boundary, a lower boundary, and an internal area, and the lower boundary includes a left boundary, a right boundary, and a bottom boundary; a person image corresponding to a person in an image stream is detected and tracked; and whether the person passes through or does not pass through the entrance is determined according to a first detection result and a second detection result.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

Abstract: A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first sub-pixel includes a first main-driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main-driving element includes a first main-gate, a first main-channel layer, a first main-source, and a first main-drain. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source, and a first sub-drain. The first capacitor electrode is electrically connected with the first main-drain and the first sub-source. The first pixel electrode is electrically connected with the first sub-drain. The common electrode and the first capacitor electrode have a first main capacitor therebetween. The common electrode and the first pixel electrode have a first sub capacitor therebetween.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: An electric motorcycle includes a transmission gear set mounted in a gearbox housing and having a power input shaft inserted through a middle block of the gearbox and a power input pulley mounted on the power input shaft, an electric motor mounted on one side of the middle block and having a motor pulley mounted on the motor shaft thereof, and a transmission belt coupled between the motor pulley and the power input pulley for enabling the electric motor to rotate the power input shaft of the transmission gear set through the transmission belt, a gear shift pedal and a gear shift axle for gear shifting, and a speed output chain gear mounted on an output shaft of the transmission gear set and driven by the output shaft to rotate the rear wheel of the electric motorcycle through a chain.

Abstract: An image processing method, comprising the following steps: obtaining a plurality of first luminance values, wherein the plurality of first luminance values corresponds to a first subpixel group comprising a target subpixel and a plurality of adjacent subpixels; and performing a subpixel rendering conversion on a target luminance value of the plurality of first luminance values corresponding to the target subpixel according to a weighting matrix and all of the plurality of first luminance values, so that the target luminance value is converted to a rendered luminance value, wherein the weighting matrix comprises a plurality of weighting parameters corresponding to the first subpixel group, and the weighting matrix is time-variant.

Abstract: A display device including backlight module, light valve groups such as display pixels disposed on the backlight module is provided, and the light valve group includes sub pixels. The backlight module includes light emitting arrays, and the light emitting array includes light emitting areas disposed along a first direction. The position of every light emitting arrays is corresponded to the position of one of the light valve groups, and the sub pixels of the light valve group are disposed along a second direction, and the first direction and the second direction are not parallel. When the light emitting areas of the light emitting array is emitting light, the illuminating light of every light emitting areas can illuminate multiple sub pixels. A driving method of the display device is also provided.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.

Abstract: A computer implemented method for detection of objects in a vicinity of a vehicle comprises the following steps carried out by computer hardware components: acquiring radar data from a radar sensor; determining a plurality of features based on the radar data; providing the plurality of features to a single detection head; and determining a plurality of properties of an object based on an output of the single detection head.

Abstract: The disclosure provides a surface-modified contact lens including a lens body, a first modification layer inside the lens body, and a second modification layer on a surface of the lens body, in which the first modification layer and the second modification layer are connected through the surface, the first modification layer and the second modification layer comprises a hydrophilic polymer, and a thickness of the first modification layer from the surface of the lens body is in a range of 1 nm to 100 nm.

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

Abstract: In one embodiment, an apparatus includes: a digital baseband circuit to receive a digital baseband signal and output a first digital baseband signal and a second digital baseband signal, the second digital baseband signal comprising a scaled version of the first digital baseband signal; a first transmitter signal path coupled to the digital baseband circuit to process the first digital baseband signal and output a first radio frequency (RF) signal; a second transmitter signal path coupled to the digital baseband circuit to process the second digital baseband signal and output a second RF signal; a first power amplifier coupled to the first transmitter signal path to amplify the first RF signal and output an amplified first RF signal; and a second power amplifier coupled to the second transmitter signal path to amplify the second RF signal and output an amplified second RF signal.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.