Abstract: Devices that convert heat into electricity, and methods for a fabrication of the same are provided. The asymmetric thermo-electrochemical capacitor uses a GO-based positive electrode and a battery-type negative electrode to open up the operating voltage window and enhance the electrical discharge capacity for converting low-grade heat into electricity with excellent efficiency, fast thermo-charging time, and stable cycles. The thermo-electrochemical device includes a carbon-based positive electrode, a conductive polymer or a metal-organic framework as negative electrode, a current collector, and a porous separator.

Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

Abstract: An electronic device which is capable of being bent in a first direction and includes a plurality of light-emitting units and a plurality of conductive patterns overlapping with at least a portion of the plurality of light-emitting units and extending in a second direction. The first direction and the second direction have an angle ? of not greater than 30 degrees.

Abstract: A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.

Abstract: A chip package is provided. The chip package includes a first substrate and a second substrate disposed over the first substrate. The first substrate and the second substrate have a lower surface and an upper surface, and the second substrate includes a first recess region surrounding the second substrate. The first recess region has a tapered sidewall and a bottom surface that is between the lower and upper surfaces of the second substrate. The chip package also includes at least one conductive pad disposed on the upper surface of the second substrate and a redistribution layer (RDL) correspondingly disposed on the conductive pad. The RDL is extended from the conductive pad onto the bottom surface of the first recess region along the tapered sidewall of the first recess region. A method of forming a chip package is also provided.

Abstract: In the penetration step, a carbon dioxide fluid is contacted to a sample of coffee green bean inside a chamber at a temperature of 28-50° C. and a pressure of 950-3,500 psi for 3-30 minutes to allow the carbon dioxide fluid to penetrate into the sample of coffee green bean. In a pressure relief step, the pressure in the chamber is reduced to normal pressure in a time period of 2-15 minutes, allowing the carbon dioxide fluid penetrated into the sample of coffee green bean to break down cell wall of the sample of coffee green bean to obtain a sample of coffee green bean with broken cell wall.

Abstract: A nano-twinned crystal film and a method thereof are disclosed. The method of fabricating a nano-twinned crystal film includes utilizing an electrolyte solution including copper salt, acid, and a water or alcohol-soluble organic additive, and performing electrodeposition, under conditions of a current density of 20˜100 mA/cm2, a voltage of 0.2˜1.0V, and a cathode-anode distance of 10˜300 mm, to form the nano-twinned crystal film on a surface at the cathode. The nano-twinned crystal film formed by the method includes a plurality of nano-twinned copper grains and a region of random crystal phases between some of adjacent nano-twinned copper grains, wherein at least some of the nano-twinned copper grains have a pillar cap configuration with a wide top and a narrow bottom.

Abstract: An electrostatic sensing system configured to sense an electrostatic information of a fluid inside a fluid distribution component and including an electrostatic sensing assembly, a signal amplifier and an analog-to-digital converter. The electrostatic sensing assembly includes a sensing component, and a shield. The sensing component is configured to be disposed at the fluid distribution component. The sensing component is disposed through the fluid distribution component so as to be partially located in the fluid distribution component. The shield surrounds a part of the sensing component that is located in the fluid distribution component. At least part of the shield is located on an upstream side of the sensing component. The signal amplifier is electrically connected to the sensing component. The analog-to-digital converter is electrically connected to the signal amplifier. The shield has an opening spaced apart from the sensing component.

Abstract: A band-pass filter (BPF) having first and second ports includes an acoustic wave filter (AWF) having first and second ports, the first port of the AWF coupled to the first port of the BPF. An impedance matching network consisting of a first inductor in parallel with a series combination of a second inductor and a capacitor is connected across the first port of the BPF.

Abstract: The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.

Abstract: A band-pass filter (BPF) having first and second ports includes an acoustic wave filter (AWF) having first and second ports, the first port of the AWF coupled to the first port of the BPF. An impedance matching network consisting of a first inductor in parallel with a series combination of a second inductor and a capacitor is connected across the first port of the BPF.

Abstract: A slicing method for horizontal facets of color 3D object includes following steps: executing a slicing procedure; calculating an intersection (4) of any polygon facet (3) of a color 3D object with one of a plurality of slicing planes (2); determining whether the polygon facet (3) is a horizontal facet; determining whether the slicing plane (2) currently processed is a highest slicing plane intersecting with the polygon facet (3) if the polygon facet (3) is determined as a horizontal facet; calculating another intersection (4) of the polygon facet (3) with next slicing plane (2) if the slicing plane (2) currently processed is not the highest slicing plane; performing a pixelated procedure to the polygon facet (3) for generating pixelated color data (5) if the slicing plane (2) currently processed is the highest slicing plane; and storing the pixelated color data (5) to a slicing file of the highest slicing plane.

Abstract: An electrostatic detecting device adapted to an object. The electrostatic detecting device includes a substrate, a sensing electrode, a dielectric layer and a ground electrode. The substrate has a first surface and a second surface opposite to the first surface. The sensing electrode is disposed on the first surface and has a sensing surface. The sensing surface faces away from the first surface and configured to face the object. The dielectric layer having a dielectric constant greater than 1 is disposed on the second surface. The ground electrode is disposed apart from the sensing electrode by a spacing. The dielectric layer is disposed between the sensing electrode and the ground electrode.

Abstract: An electrostatic measuring method for an inner wall of a fluid pipeline includes a step of disposing a grounded metal plate to an outer wall of the fluid pipeline; a step of forming a grounding effect through the grounded metal plate and the outer wall, wherein the grounded metal plate has induced charges, the induced charges combine outer-wall existing charges on the outer wall to form total outer-wall charges, and the total outer-wall charges are related to charges to be measured on the inner wall of the fluid pipeline; and, a step of measuring an electrostatic voltage above the grounded metal plate so as to obtain the charges to be measured on the inner wall of the fluid pipeline. In addition, an electrostatic measuring system for inner wall of fluid pipeline is also provided.

Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

Abstract: A printing method for color compensation adopted by a 3D printer (1) having a 3D nozzle (121) and a 2D nozzle (122) is disclosed. The printing method includes following steps of: controlling the 3D nozzle (121) to print a slicing object (2) of the 3D object upon a printing platform (11) according to a route file; controlling the 2D nozzle (122) to perform coloring on the printed slicing object (2) according to an image file; controlling the 2D nozzle (122) and the printing platform (1) to rotate relatively for creating an angular transposition between the 2D nozzle (122) and the printing platform (1) after the slicing object (2) is colored completely; and, controlling the 2D nozzle (122) to again perform coloring on the colored slicing object (2) after the 2D nozzle (2) and the printing platform (11) rotated relatively.

Abstract: A 3D slicing and printing method using strengthened auxiliary wall is provided. The method is to control a 3D printer (3) to retrieve multiple layers of object print data corresponding to a 3D object (90), and multiple layers of wall print data and raft print data, print multiple layers of raft slice physical models (400,60) on a print platform (307) layer by layer according to the raft print data, print multiple layers of wall slice physical models (420-421,80-81) on the printed raft slice physical models (400,60) layer by layer according to the wall print data, and print multiple layers of 3D slice physical models (50-53,70-71) layer by layer according to the object print data during printing the raft slice physical models (400,60) and the wall slice physical models (420-421,80-81). It can effectively prevent the auxiliary wall (42,8) from collapsing and failure of printing a whole 3D physical model (5,7) via making a raft structure (40,6) be arranged under the auxiliary wall (42,8).