Patents by Inventor Yu Tso Lin

Yu Tso Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395948
    Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.
    Type: Application
    Filed: August 26, 2020
    Publication date: December 17, 2020
    Inventor: Yu-Tso LIN
  • Patent number: 10855291
    Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
  • Publication number: 20200357792
    Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Publication number: 20200357801
    Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.
    Type: Application
    Filed: July 12, 2019
    Publication date: November 12, 2020
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yu-An Chen, Shih-Siang Chen, Shih-Ping Lee, Yi-Nung Lin, Po-Yi Wu, Chen-Tso Han, Bo-An Tsai
  • Patent number: 10763876
    Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Tso Lin
  • Patent number: 10756083
    Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10642227
    Abstract: A digital-to-time converter (DTC) includes a plurality of delay stages connected in series, in which each of the plurality of delay stages includes an input circuit and a delay circuit. The input circuit has a first input terminal, a second input terminal and a first output terminal, and is configured to receive a clock signal through the first input terminal, receive a digital control signal through the second input terminal, generate an output signal according to the clock signal and the digital control signal, and output the output signal to the first output terminal of the input circuit. The delay circuit is coupled to the input circuit in series, and is configured to receive the output signal and an input signal, and generate a delay signal according to the output signal and the input signal. The delay signal indicates a time interval corresponding to the digital control signal.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Tso Lin
  • Publication number: 20200136632
    Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 30, 2020
    Inventor: Yu-Tso LIN
  • Publication number: 20190355921
    Abstract: An organic light-emitting device includes a first electrode layer, an emission layer, an electron transporting layer, an electron injection layer, and a second electrode layer sequentially formed from bottom to top. The emission layer includes a guest light-emitting material, a first phenyl phosphine oxide derivative and a hole transporting material. The electron transporting layer includes a second phenyl phosphine oxide derivative and a third phenyl phosphine oxide derivative different from the second phenyl phosphine oxide derivative. One of the second phenyl phosphine oxide derivative and the third phenyl phosphine oxide derivative is identical to the first phenyl phosphine oxide derivative. The electron injection layer includes an alkaline metal compound.
    Type: Application
    Filed: January 29, 2019
    Publication date: November 21, 2019
    Inventors: Hsin-Fei MENG, Sheng-Fu HORNG, Yu-Chiang CHAO, Chih-Yu CHANG, Yu-Fan CHANG, Mei-Peng LIOU, Qian-Wei LIN, Hsiao-Tso SU, Chiung -Wen CHANG
  • Patent number: 10277117
    Abstract: A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Publication number: 20180342948
    Abstract: A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 29, 2018
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Publication number: 20180342495
    Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 29, 2018
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10128211
    Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 13, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Wei Chang, Yong-Cheng Chuang, Yu-Tso Lin
  • Publication number: 20180211936
    Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.
    Type: Application
    Filed: June 22, 2017
    Publication date: July 26, 2018
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chang, Yong-Cheng Chuang, Yu-Tso Lin
  • Patent number: 9857824
    Abstract: A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of the first transistor, and (iii) a second terminal that has a voltage VG2 and is coupled to a gate of the second transistor. A comparator has a first input that is coupled to the resistor's second terminal. A diode-connected reference transistor is connected from the voltage rail to the comparator's second input to apply a voltage VD at the second input. An adjusting circuit adjusts the digital resistance-controlling value to cause VG2 to approach VD until the comparator's output changes state when VG2 reaches VD.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Yu-Tso Lin
  • Publication number: 20170357284
    Abstract: A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of the first transistor, and (iii) a second terminal that has a voltage VG2 and is coupled to a gate of the second transistor. A comparator has a first input that is coupled to the resistor's second terminal. A diode-connected reference transistor is connected from the voltage rail to the comparator's second input to apply a voltage VD at the second input. An adjusting circuit adjusts the digital resistance-controlling value to cause VG2 to approach VD until the comparator's output changes state when VG2 reaches VD.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventor: Yu-Tso Lin
  • Patent number: 9154144
    Abstract: A phase-locked loop includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer. The first semiconductor layer has formed thereon a phase frequency detector circuit having a reference frequency input, a feedback frequency input, an up output and a down output, a charge pump circuit having a first input coupled to the up output and a second input coupled to the down output, and an output, and a loop filter circuit coupled to the charge pump. The second semiconductor layer has formed thereon a voltage controlled oscillator having an input and an output, and a feedback frequency divider circuit having an input coupled to the output of the voltage controlled oscillator and an input. A first interlayer via couples the loop filter circuit to the input of the voltage controlled oscillator circuit. A second interlayer via couples the output of the feedback frequency divider circuit to the feedback input of the phase frequency detector.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Tso Lin
  • Patent number: 9065454
    Abstract: A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Tso Lin
  • Publication number: 20150171873
    Abstract: A phase-locked loop includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer. The first semiconductor layer has formed thereon a phase frequency detector circuit having a reference frequency input, a feedback frequency input, an up output and a down output, a charge pump circuit having a first input coupled to the up output and a second input coupled to the down output, and an output, and a loop filter circuit coupled to the charge pump. The second semiconductor layer has formed thereon a voltage controlled oscillator having an input and an output, and a feedback frequency divider circuit having an input coupled to the output of the voltage controlled oscillator and an input. A first interlayer via couples the loop filter circuit to the input of the voltage controlled oscillator circuit. A second interlayer via couples the output of the feedback frequency divider circuit to the feedback input of the phase frequency detector.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 18, 2015
    Inventor: Yu-Tso LIN
  • Publication number: 20140145769
    Abstract: A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.
    Type: Application
    Filed: February 22, 2013
    Publication date: May 29, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Tso Lin