Patents by Inventor Yu Tso Lin
Yu Tso Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947373Abstract: The present disclosure provide an electronic device. The electronic device includes a voltage generator and a low drop-out (LDO) circuit. The voltage generator has an input and an output. The LDO circuit has an input electrically connected to the output of the voltage generator. The voltage generator includes a first voltage regulator having a first terminal and a second terminal. The first terminal of the first voltage regulator is electrically connected to the output of the voltage generator.Type: GrantFiled: January 13, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Tso Lin, Min-Shueh Yuan
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Patent number: 11888490Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: GrantFiled: February 14, 2023Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Publication number: 20240022255Abstract: An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.Type: ApplicationFiled: July 25, 2023Publication date: January 18, 2024Inventors: Min-Shueh YUAN, Chao-Chieh LI, Chia-Chun LIAO, Yu-Tso LIN, Wen-Yuan TSAI, Chih-Hsien CHANG
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Publication number: 20230387105Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
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Publication number: 20230384373Abstract: An electronic circuit and a method of error correction are provided. The electronic circuit includes a time-to-digital converter (TDC) and an error cancelation circuit. The TDC is configured to generate a first signal. The error cancelation circuit is configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal. The number of transitions within the second signal is less than the number of transitions within the first signal.Type: ApplicationFiled: May 30, 2022Publication date: November 30, 2023Inventors: CHIA-CHUN LIAO, CHAO CHIEH LI, YU-TSO LIN, MIN-SHUEH YUAN
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Patent number: 11764211Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.Type: GrantFiled: July 23, 2020Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
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Patent number: 11742865Abstract: An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.Type: GrantFiled: January 31, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Wen-Yuan Tsai, Chih-Hsien Chang
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Publication number: 20230221743Abstract: The present disclosure provide an electronic device. The electronic device includes a voltage generator and a low drop-out (LDO) circuit. The voltage generator has an input and an output. The LDO circuit has an input electrically connected to the output of the voltage generator. The voltage generator includes a first voltage regulator having a first terminal and a second terminal. The first terminal of the first voltage regulator is electrically connected to the output of the voltage generator.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Inventors: YU-TSO LIN, MIN-SHUEH YUAN
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Publication number: 20230198529Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: ApplicationFiled: February 14, 2023Publication date: June 22, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Patent number: 11616508Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: GrantFiled: November 18, 2021Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Publication number: 20230052899Abstract: An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.Type: ApplicationFiled: January 31, 2022Publication date: February 16, 2023Inventors: Min-Shueh YUAN, Chao-Chieh LI, Chia-Chun LIAO, Yu-Tso LIN, Wen-Yuan TSAI, Chih-Hsien CHANG
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Publication number: 20220077861Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: ApplicationFiled: November 18, 2021Publication date: March 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Patent number: 11184009Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: GrantFiled: October 29, 2020Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Publication number: 20210305988Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: ApplicationFiled: October 29, 2020Publication date: September 30, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Patent number: 11005464Abstract: The disclosure provides a delay line circuit including an output stage. The output stage includes a first inverter cell, a second inverter cell, a correction circuit, and a first switch capacitor array. The input terminal of the first inverter cell receives a reference clock signal. The input terminal of the second inverter cell is coupled with the output terminal of the first inverter cell. The first terminal of the correction circuit is coupled with the output terminal of the first inverter cell, and the second terminal of the correction circuit is coupled with a ground, wherein the correction circuit corrects a duty cycle of the delay line circuit. The first terminal of the first switch capacitor array is coupled with the output terminal of the second inverter cell, and the second terminal of the first switch capacitor array is coupled with the ground.Type: GrantFiled: March 26, 2020Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yu-Tso Lin
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Patent number: 11005488Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.Type: GrantFiled: August 26, 2020Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Tso Lin
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Publication number: 20200395948Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.Type: ApplicationFiled: August 26, 2020Publication date: December 17, 2020Inventor: Yu-Tso LIN
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Patent number: 10855291Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.Type: GrantFiled: March 30, 2020Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
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Publication number: 20200357792Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
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Patent number: 10763876Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.Type: GrantFiled: September 18, 2019Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Tso Lin