Patents by Inventor Yu Wei

Yu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150398
    Abstract: A method for controlling transmission control protocol performance in a wireless network is provided. The method is used in a server device and the server device is in communication with a client device based on a TCP connection. The method includes receiving a plurality of packets from a TCP layer in the server device. The method includes storing the packets in a buffer, recording the packets in a transmission list, and forwarding the packets to the client device, wherein each packet has a packet sequence number. In response to receiving a packet acknowledgment message sent from the client device, the method includes determining a packet loss rate of the client device based on the packet acknowledgment message. The method includes dynamically adjusting a congestion window size of the TCP connection based on the packet loss rate to control a transmission rate of the TCP layer.
    Type: Application
    Filed: March 18, 2024
    Publication date: May 8, 2025
    Inventors: Yu-Wei LEE, Yi-An CHEN, Hsiang-Ting FANG
  • Publication number: 20250147544
    Abstract: An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal, a frequency divider configured to receive the clock signal and generate a reduced frequency signal indicative of a skew of a first multi-phase clock signal, and a delay line control circuit configured to adjust the skew of the first multi-phase clock signal by comparing the reduced frequency signal with a predetermined duty cycle, and generating a control signal to modify a delay applied to the first multi-phase clock signal.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Inventor: Yu-Wei Lin
  • Publication number: 20250143446
    Abstract: An outdoor leisure-purpose table frame includes a tabletop including a through hole; a number of table legs detachably mounted on an undersurface of the tabletop; and a hole-diameter adjusting module detachably mounted in the through hole. The present invention is easy to knock down and carry and provides a hole-diameter adjusting module to allow the user to insert various objects of different diameters in the present invention. The present invention further provides clamp units for clamping and securely holding the objects to be inserted and each of the table legs. The present invention is usable in combination with an outdoor clamping tool to enhance the stability and steadiness of the present invention.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventor: YU-WEI TAI
  • Publication number: 20250149379
    Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A shallow trench isolation (STI) region is formed around a lower portion of the semiconductor fin. An STI protection layer is over the STI region. After forming the STI protection layer, source/drain recesses are etched in the semiconductor fin. Source/drain epitaxial regions are formed in the source/drain recesses.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hung CHEN, Yen-Chun HUANG, Yu-Wei CHOU, Zhen-Cheng WU
  • Publication number: 20250149086
    Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventors: YU-WEI LIN, MENG-SHENG CHANG
  • Publication number: 20250146319
    Abstract: An easy-to-carry outdoor leisure-purpose bracket includes a main body that includes two clamp arms each having a closed end and an open end, the closed ends being combined together and formed with at least one clamping hole perpendicular to the clamp arms, one of the clamp arms being formed with a retaining engagement portion protruded toward another one of the clamp arms, the another one of the clamp arms being recessed to form a notch corresponding to the retaining engagement portion; a locking unit, which is arranged on the main body at a predetermined location and is operable to selectively close the clamp arms together; and two fixing units, which are respectively and rotatably mounted on the open ends of the clamp arms, and each is operable to attach the main body to a surface in a removable manner.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventor: YU-WEI TAI
  • Publication number: 20250142845
    Abstract: A device structure includes a first electrode overlying a substrate; a node dielectric contacting the first electrode and including a dielectric material having a dielectric constant greater than 30; and a second electrode contacting the node dielectric. A first one of the first electrode and the second electrode includes a first catalytic metal plate in direct contact with the node dielectric and having a first electronegativity that is not greater than an electronegativity of molybdenum.
    Type: Application
    Filed: April 21, 2024
    Publication date: May 1, 2025
    Inventors: Kuen-Yi Chen, Yi Ching Ong, Wei Ting Hsieh, Yu-Wei Ting, Kuo-Ching Huang
  • Publication number: 20250140643
    Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Li, Chun-Yen Lan, Yu-Wei Lin, Sheng-Hsiang Chiu, Tzu-Ting Chou, Pei-Hsuan Lee, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 12288689
    Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.
    Type: Grant
    Filed: July 3, 2022
    Date of Patent: April 29, 2025
    Assignee: Winbond Electronics Corp.
    Inventors: Pei-Hsiu Peng, Hung-Yu Wei
  • Patent number: 12288820
    Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 12288798
    Abstract: An image sensor includes a pixel array, a dielectric layer, a plurality of first conductive shielding regions, and a plurality of second conductive shielding regions. The pixel array includes photodiodes within a substrate. The dielectric layer is over the substrate. From a plan view, the first conductive shielding regions are adjacent four corners of the pixel array, and the second conductive shielding regions are adjacent four sides of the pixel array. The second conductive region has a length-to-width ratio greater than a length-to-width ratio of the first conductive region.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Volume Chien, Su-Hua Chang, Chia-Yu Wei, Zen-Fong Huang, Chi-Cherng Jeng
  • Patent number: 12289865
    Abstract: A two-phase immersion-cooling heat-dissipation composite structure. The heat-dissipation composite structure includes a heat dissipation base, a plurality of high-thermal-conductivity fins, and at least one high-porosity solid structure. The heat dissipation base has a first surface and a second surface that face away from each other. The second surface of the heat dissipation base is in contact with a heating element immersed in a two-phase coolant. The first surface of the heat dissipation base is connected to the high-thermal-conductivity fins. The at least one high-porosity solid structure is located at the first surface of the heat dissipation base, and is connected and alternately arranged between side walls of two adjacent ones of the high-thermal-conductivity fins. Each of the high-porosity solid structure includes a plurality of closed holes and a plurality of open holes.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: April 29, 2025
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Chun-Te Wu, Ching-Ming Yang, Yu-Wei Chiu, Tze-Yang Yeh
  • Publication number: 20250132516
    Abstract: A connection cable (1) includes an insulation seat (10), a circuit board (20) and a protection cover (30). The insulation seat (10) includes a main body (11) formed with a slot (110) and a conduction opening (111). The conduction opening (111) is connected to the slot (110) and located on the bottom side of the main body (11). The circuit board (20) includes a substrate (21) and a plurality of conductive portions (22) disposed on the substrate (21). The substrate (21) is inserted in the slot (110). The conductive portions (22) are exposed from the conduction opening (111). The protection cover (30) is combined on the main body (11) to shield the conduction opening (111). The protection cover (30) is pushed by the dock connector (2) to expose the conduction opening (111) and to be separated from the main body (11).
    Type: Application
    Filed: December 4, 2023
    Publication date: April 24, 2025
    Inventors: Shang-Yen HUANG, Wei-Wen CHAN, Yu-Wei CHOU
  • Publication number: 20250133774
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 24, 2025
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Patent number: 12284804
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Perng-Fei Yuh, Yih Wang, Meng-Sheng Chang, Jui-Che Tsai, Ku-Feng Lin, Yu-Wei Lin, Keh-Jeng Chang, Chansyun David Yang, Shao-Ting Wu, Shao-Yu Chou, Philex Ming-Yan Fan, Yoshitaka Yamauchi, Tzu-Hsien Yang
  • Patent number: 12283851
    Abstract: A hairpin stator includes a core, slot-positions and hairpin wires. The core includes a first side and a second side. The slot-positions are configured on the core circumferentially to form M radially-adjacent slot-position layers, wherein M is an odd number greater than or equal to 5. The hairpin wires are configured in the slot-positions and connected to form a plurality of windings. The hairpin wires include a plurality of first U-shaped wires arranged at an outermost slot-position layer in the radial direction and a plurality of second U-shaped wires arranged at an innermost slot-position layer in the radial direction. Each first U-shaped wire includes a U-shaped section arranged at the outermost slot-position layer and protruding from the first side of the core. Each second U-shaped wire includes a U-shaped section arranged at the innermost slot-position layer and protruding from the second side of the core.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: April 22, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Wei Chuang, Yao-Hsien Shao, Ji Dai, Tzu-Ting Hsu, Yen-Wei Tseng
  • Publication number: 20250121078
    Abstract: Disclosed are compounds of formula (I): in which L1, L2, LD1, LD2, R5, and R6 are defined. Also provided are pharmaceutical compositions containing such a compound a method of treating cancer using the compound.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 17, 2025
    Inventors: Lun Kelvin Tsou, Yu-Wei Liu, Chiung-Tong Chen, Tai-Yu Chiu, Chuan Shih, Jang-Yang Chang
  • Publication number: 20250126840
    Abstract: The present disclosure describes a semiconductor device having a source/drain dielectric. The semiconductor device includes a channel structure on a substrate, a dielectric structure on the substrate and adjacent to the channel structure, and an epitaxial structure on a top surface of the dielectric structure. The epitaxial structure is in contact with the channel structure.
    Type: Application
    Filed: February 6, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu WEI, Cheng-I LIN, Shu-Han CHEN, Chi On CHUI
  • Patent number: 12278506
    Abstract: A wireless management system includes a controller and energy storage units. Each of the energy storage units includes an energy storage device and a node substrate. The wireless management system is configured to select a first node substrate from the node substrates based on a signal strength of each of first request signals to join a local network by the controller. The wireless management system is further configured to select a second node substrate from the node substrates based on the signal strength of each of second request signals to join the local network by the first node substrate. The wireless management system is further configured to assign a serial number corresponds to each of the energy storage units based on the local network by the controller.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: April 15, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Wei Lee, Chih-Kuan Yen, Chin-Ming Chen
  • Patent number: 12275629
    Abstract: A fluid material dispensing apparatus includes: a target nozzle for dispensing water to a target container; a water drainage port; a temperature adjustment device for adjusting a temperature of received water to produce a temperature-adjusted water; a flow direction control device coupled with target nozzle, the temperature adjustment device, and the water drainage port; and a control circuit. When the control circuit determines that a temperature of the temperature-adjusted water reaches a predetermined temperature, the control circuit controls the flow direction control device to guide the temperature-adjusted water to flow toward the target nozzle through the first output terminal, so that the target nozzle dispenses the temperature-adjusted water into the target container.
    Type: Grant
    Filed: July 3, 2024
    Date of Patent: April 15, 2025
    Assignee: Botrista, Inc.
    Inventors: Wu-Chou Kuo, Yu-Min Lee, Yu Wei Chen