Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.

Abstract: An image sensor includes a pixel array, a dielectric layer, a plurality of first conductive shielding regions, and a plurality of second conductive shielding regions. The pixel array includes photodiodes within a substrate. The dielectric layer is over the substrate. From a plan view, the first conductive shielding regions are adjacent four corners of the pixel array, and the second conductive shielding regions are adjacent four sides of the pixel array. The second conductive region has a length-to-width ratio greater than a length-to-width ratio of the first conductive region.

Abstract: A two-phase immersion-cooling heat-dissipation composite structure. The heat-dissipation composite structure includes a heat dissipation base, a plurality of high-thermal-conductivity fins, and at least one high-porosity solid structure. The heat dissipation base has a first surface and a second surface that face away from each other. The second surface of the heat dissipation base is in contact with a heating element immersed in a two-phase coolant. The first surface of the heat dissipation base is connected to the high-thermal-conductivity fins. The at least one high-porosity solid structure is located at the first surface of the heat dissipation base, and is connected and alternately arranged between side walls of two adjacent ones of the high-thermal-conductivity fins. Each of the high-porosity solid structure includes a plurality of closed holes and a plurality of open holes.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.

Abstract: A connection cable (1) includes an insulation seat (10), a circuit board (20) and a protection cover (30). The insulation seat (10) includes a main body (11) formed with a slot (110) and a conduction opening (111). The conduction opening (111) is connected to the slot (110) and located on the bottom side of the main body (11). The circuit board (20) includes a substrate (21) and a plurality of conductive portions (22) disposed on the substrate (21). The substrate (21) is inserted in the slot (110). The conductive portions (22) are exposed from the conduction opening (111). The protection cover (30) is combined on the main body (11) to shield the conduction opening (111). The protection cover (30) is pushed by the dock connector (2) to expose the conduction opening (111) and to be separated from the main body (11).

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A hairpin stator includes a core, slot-positions and hairpin wires. The core includes a first side and a second side. The slot-positions are configured on the core circumferentially to form M radially-adjacent slot-position layers, wherein M is an odd number greater than or equal to 5. The hairpin wires are configured in the slot-positions and connected to form a plurality of windings. The hairpin wires include a plurality of first U-shaped wires arranged at an outermost slot-position layer in the radial direction and a plurality of second U-shaped wires arranged at an innermost slot-position layer in the radial direction. Each first U-shaped wire includes a U-shaped section arranged at the outermost slot-position layer and protruding from the first side of the core. Each second U-shaped wire includes a U-shaped section arranged at the innermost slot-position layer and protruding from the second side of the core.

Abstract: The present disclosure describes a semiconductor device having a source/drain dielectric. The semiconductor device includes a channel structure on a substrate, a dielectric structure on the substrate and adjacent to the channel structure, and an epitaxial structure on a top surface of the dielectric structure. The epitaxial structure is in contact with the channel structure.

Abstract: Disclosed are compounds of formula (I): in which L1, L2, LD1, LD2, R5, and R6 are defined. Also provided are pharmaceutical compositions containing such a compound a method of treating cancer using the compound.

Abstract: A wireless management system includes a controller and energy storage units. Each of the energy storage units includes an energy storage device and a node substrate. The wireless management system is configured to select a first node substrate from the node substrates based on a signal strength of each of first request signals to join a local network by the controller. The wireless management system is further configured to select a second node substrate from the node substrates based on the signal strength of each of second request signals to join the local network by the first node substrate. The wireless management system is further configured to assign a serial number corresponds to each of the energy storage units based on the local network by the controller.

Abstract: A fluid material dispensing apparatus includes: a target nozzle for dispensing water to a target container; a water drainage port; a temperature adjustment device for adjusting a temperature of received water to produce a temperature-adjusted water; a flow direction control device coupled with target nozzle, the temperature adjustment device, and the water drainage port; and a control circuit. When the control circuit determines that a temperature of the temperature-adjusted water reaches a predetermined temperature, the control circuit controls the flow direction control device to guide the temperature-adjusted water to flow toward the target nozzle through the first output terminal, so that the target nozzle dispenses the temperature-adjusted water into the target container.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

Abstract: The invention provides an automatic stirring device in the field of fluid machinery and bioreactors, focusing on enhancing fluid control efficiency and consistency in biological cultivation processes. It utilizes a flexible channel body or reactor body to facilitate the flow of nutrient solution along specific channels (such as S-shaped flexible channels or S-shaped loop channels), designed to reduce shear forces and achieve iso-level uniform flow. A power system and monitoring and control system are employed to regulate the flow of nutrient solution and monitor cultivation conditions in real-time, thus supporting various bioprocess cultivation requirements.

Abstract: The present invention provides for a genetically modified host cell comprising a first polypeptide capable of active transport of urea into the host cell and/or a second polypeptide capable of degrading urea into ammonia and carbon dioxide, wherein the genetically modified host cell is capable of degrading urea into ammonia and carbon dioxide. The genetically modified host cell in a medium comprising urea, a calcium salt or calcium ion, and a phosphate is capable of producing calcium phosphate.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: An audio dose monitoring circuit includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: Changing a lighting mode for a human interface device is described herein. A first lighting mode can be initiated for a human interface device. Keys on the human interface device can be selected over a period of time at a frequency that is within a defined range. A second lighting mode for the human interface device can be identified based in part on the frequency being within the defined range. The first lighting mode and the second lighting mode can define a lighting scheme for light sources in the human interface device that reflect a user mood. The first lighting mode can be switched to the second lighting mode.

Abstract: A method of forming a semiconductor memory device includes: forming a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternatingly stacked in a Z direction substantially perpendicular to the substrate; forming a plurality of source/drain trenches in the stack structure; conformally forming a barrier layer in the source/drain trenches, and then filling the source/drain trenches with a plurality of sacrificial segments; forming a protection layer over the stack structure to cover the barrier layer and the sacrificial segments; removing the sacrificial layers of the stack structure to form a plurality of spaces among the dielectric layers; forming a plurality of conductive layers in the spaces; sequentially removing the protection layer, the sacrificial segments and the barrier layer; and forming a plurality of memory structures in the source/drain trenches.