Patents by Inventor Yu-Wei Chen

Yu-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031286
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Publication number: 20210168405
    Abstract: A method and apparatus of video encoding video coding for a video encoder or decoder using Neural Network (NN) are disclosed. According to this method, the multiple frames in a video sequence comprises multiple segments, where each of the multiple segments comprises a set of frames. The NN (Neural Network) processing is applied to a target signal in one or more encoded frames of a target segment in the encoder side or to the target signal in one or more decoded frames of the target segment in the decoder side using one NN parameter set for the target segment. The target signal may correspond to reconstructed residual, reconstructed output, de-blocked output, SAO (sample adaptive offset) output, ALF (adaptive loop filter) output, or a combination thereof. In another embodiment, the NN processing is applied to a target signal only in one or more specific encoded or decoded frames.
    Type: Application
    Filed: April 16, 2019
    Publication date: June 3, 2021
    Inventors: Yu-Ling HSIAO, Yu-Chi SU, Jan KLOPP, Ching-Yeh CHEN, Tzu-Der CHUANG, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 11024593
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Patent number: 11024616
    Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
  • Patent number: 11025010
    Abstract: An electrical connector includes an insulative housing and a plurality of contacts retained therein. The housing forms a central slot along a longitudinal direction, and includes a base, opposite first wall and second wall extending from the base and located by two sides of the central slot. The contact includes a retaining section retained to the corresponding first or second wall, and a spring arm with a contacting section at a free end, extending from the retaining section and into the central slot wherein a width/thickness ratio in the contacting section is set within a range between 0.8˜1.28.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 1, 2021
    Assignees: FU DING PRECISION INDUSTRIAL (ZHENGZHOU) CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Shih-Wei Hsiao, Yu-San Hsiao, Yen-Chih Chang, Na Yang, Meng Liu, Yu-Ke Chen
  • Publication number: 20210160734
    Abstract: A channel loading pre-adjusting system for 5G wireless communication adapted to be used for communicating at least one user's device with a core network includes a radio unit, a distributed unit in communication with the radio unit via a specified transmission channel, and a central unit. The distributed unit periodically detects transmission conditions of the specified channel and determines whether to issue an alarm signal accordingly, and in response to the alarm signal, the central unit determines whether to suspend data transmission via the specified transmission channel. The transmission conditions include a first group of latency parameters realized in a first number of consecutive detecting operations of the distributed unit and a temporal threshold derived from a second group of latency parameters realized in a second number of consecutive detecting operations of the distributed unit, and the first group of latency parameters are dynamically updated with time.
    Type: Application
    Filed: December 19, 2019
    Publication date: May 27, 2021
    Inventors: YU-HSIN KUO, REN-HAO CHEN, PO-WEN TUAN, YAN-WEI LIU
  • Publication number: 20210159325
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
  • Publication number: 20210160528
    Abstract: A video decoder determines whether the current block is coded by using intra block copy mode. The video decoder identifies a list of one or more prediction candidates for the current block. When the current block is not coded by using intra block copy mode, one or more spatial neighbors of the current block that are positioned in a same MER as the current block are excluded from the list of prediction candidates. When the current block is coded by using intra block copy mode and the list of prediction candidates belongs to a predefined subset of multiple different candidate lists, at least one of the identified prediction candidates is a spatial neighbor of the current block that is positioned in the MER. The video decoder reconstructs the current block by using a prediction candidate selected from the list of prediction candidates to generate a prediction of the current block.
    Type: Application
    Filed: November 26, 2020
    Publication date: May 27, 2021
    Inventors: Chun-Chia Chen, Yu-Ling Hsiao, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
  • Publication number: 20210160482
    Abstract: Video processing methods and apparatuses for processing a current block in a current picture include receiving input data of the current block, determining a reference picture, determining whether picture sizes of the current and reference pictures are different, determining whether horizontal wraparound motion compensation is enabled for predicting the current block, performing motion compensation for the current block to obtain a reference block from the reference picture, and encoding or decoding the current block according to the reference block. Horizontal wraparound motion compensation is disabled when the picture sizes of the current and reference pictures are different.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Inventors: Chih-Yao CHIU, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Yu-Wen HUANG, Tzu-Der CHUANG
  • Patent number: 11002942
    Abstract: An optical imaging lens including a first, a second, a third, a fourth, a fifth, and a sixth lens elements arranged in sequence from an object side to an image side. Each of the lens elements includes an object-side surface and an image-side surface. The first to sixth lens elements have refracting power. The second lens element has a negative refracting power. An optical axis region of the image-side surface of the third lens element is concave. There is no air gap between the fourth lens element and the fifth lens element. A ratio between a distance on an optical axis from the image-side surface of the first lens element to the object-side surface of the fourth lens element and a thickness of the first lens element along the optical axis is less than or equal to 3.000.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 11, 2021
    Assignee: GENIUS ELECTRONICS OPTICAL CO., LTD.
    Inventors: Yu-Ming Chen, Pei-Chi Wang, Sheng-Wei Hsu
  • Patent number: 11005643
    Abstract: A communication receiving device includes a clock data recovery circuit, an analog-to-digital converter (ADC), a channel evaluating circuit, a first equalizer, and a selector. The clock data recovery circuit is configured to generate a clock signal according to a first digital signal. The ADC is coupled to the clock data recovery circuit, and configured to convert a first analog signal to a second digital signal according to the clock signal. The channel evaluating circuit is configured to analyze the second digital signal to output a selection signal. The first equalizer is coupled to the ADC, and configured to equalize the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer, the ADC, and the clock data recovery circuit. The selector is configured to output the second digital signal or the third digital signal as the first digital signal according to the selection signal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 11, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Hsun-Wei Kao
  • Publication number: 20210132406
    Abstract: A mechanism to render a lens module immune to trembling and jarring includes a carrier, a support element movably mounted on the carrier, and a driving element. The driving element includes a conductive structure arranged on the carrier, a plurality of positive pads on the carrier, and a plurality of shape memory alloy (SMA) wires. The SMA wires are electrically connected to the positive pads and the conductive structure. When currents flow into the SMA wires via the positive pads, the SMA wires deform upon heating and pull on the conductive structure, thus the conductive structure drives the support element to rotate in a plane parallel to the carrier. A lens module and an electronic device including the mechanism are also disclosed.
    Type: Application
    Filed: December 2, 2019
    Publication date: May 6, 2021
    Inventors: YU-SHUAI LI, SHIN-WEN CHEN, JING-WEI LI, JIAN-CHAO SONG, SHENG-JIE DING
  • Publication number: 20210136400
    Abstract: A method and apparatus of video coding using Merge mode or Skip mode in a video coding system are disclosed. According to this method, a Merge or Skip candidate list is generated from multiple-type candidates comprising one or more sub-block TMVP-type (temporal motion vector prediction-type) candidates. The step of generating a Merge or Skip candidate list comprises a pruning process dependent on whether a current sub-block TMVP-type candidate being inserted, a previous sub-block TMVP-type candidate in the Merge or Skip candidate list, or both are “single block”. According to another method, a Merge or Skip candidate list is generated from multiple-type candidates including sub-block TMVP-type (temporal motion vector prediction-type) candidates, where the sub-block TMVP-type candidates comprise two or more first sub-block temporal MV predictors.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 6, 2021
    Inventors: Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20210127042
    Abstract: A camera module includes a composite base, an optical lens arranged at a first side of the composite base; and a circuit board arranged at a second side of the composite base. The composite base includes a metal frame and a plastic frame. The metal frame includes a plurality of first metal strips connected end to end and at least one second metal strip corresponding extending from part of the plurality of first metal strips. The plastic frame includes a plurality of first plastic strips connected end to end and at least one second plastic strip extending from part of the plurality of first plastic strip. The first plastic strips are fixed to the first metal strips to form a top wall of the composite base, and the second plastic strips are connected to the second metal strips to form a side wall of the composite base.
    Type: Application
    Filed: May 6, 2020
    Publication date: April 29, 2021
    Inventors: JIAN-CHAO SONG, SHENG-JIE DING, JING-WEI LI, SHIN-WEN CHEN, YU-SHUAI LI
  • Publication number: 20210125836
    Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 29, 2021
    Inventors: Kuan-Wei Huang, Yu-Yu Chen, Jyu-Horng Shieh
  • Publication number: 20210120711
    Abstract: A picking apparatus is configured to pick up a plurality of micro elements. The picking apparatus includes a main body and a plurality of picking portions. The picking portions connect with and protrude from the main body. Each of the picking portions has a first surface. The first surfaces are away from the main body and configured to pick up the micro elements. The main body has a second surface at least partially located between the picking portions. Each of the first surfaces has a first viscosity. The second surface has a second viscosity. The second viscosity is less than the first viscosity.
    Type: Application
    Filed: November 25, 2019
    Publication date: April 22, 2021
    Inventors: Chi-Wei LIU, Fu-Hsin CHEN, Yu-Chun LEE
  • Publication number: 20210119438
    Abstract: An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.
    Type: Application
    Filed: May 13, 2020
    Publication date: April 22, 2021
    Inventors: Yu-Jen Cheng, Chih-Wei Mu, Sheng-Tsung Chen, Chieh-Min Lo, Wei-Chung Chang
  • Patent number: 10985125
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
  • Publication number: 20210005567
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Shu-Chia HSU, Leu-Jen CHEN, Yi-Wei LIU, Shang-Yun HOU, Jui-Hsieh LAI, Tsung-Yu CHEN, Chien-Yuan HUANG, Yu-Wei CHEN
  • Publication number: 20200365571
    Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang