Abstract: A circuit board assembly for electronic devices includes a circuit board having a first surface and a second surface opposite the first surface, and a heat sink carrier disposed on the first surface of the circuit board. The heat sink carrier includes at least one clamp portion. The assembly also includes a heat sink. The heat sink is positioned in the at least one clamp portion of the heat sink carrier to transfer heat from one or more electronic devices to the heat sink via the heat sink carrier.

Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.

Abstract: The present disclosure provides an operating method of a system for analyzing brain tissue based on computerized tomographic imaging, and the operation method includes steps as follows. A computed tomography image of a subject is aligned to a predetermined standard brain space image, to obtain a first normalized test computed tomography image. A voxel contrast of the first normalized test computed tomography image is enhanced to obtain an enhanced first normalized test computed tomography image. The enhanced first normalized test computed tomography image is aligned to an average computed tomographic image of a control group to obtain a second normalized test computed tomography image. An analysis based on the second normalized test computed tomography image and a plurality of computerized tomographic images of the control group is performed to obtain a t-score map.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A circuit board assembly for electronic devices includes a circuit board having a first surface and a second surface opposite the first surface, and a heat sink carrier disposed on the first surface of the circuit board. The heat sink carrier includes at least one clamp portion. The assembly also includes a heat sink. The heat sink is positioned in the at least one clamp portion of the heat sink carrier to transfer heat from one or more electronic devices to the heat sink via the heat sink carrier.

Abstract: The present disclosure provides an operating method of an automatic brain infarction detection system on magnetic resonance imaging (MRI), which includes steps as follows. Images corresponding to different slices of a brain of a subject are received from the MRI machine. The image mask process is performed on first and second images of the images. It is determined whether the cerebellum image intensity and the brain image intensity in the first image are matched. When the cerebellum image intensity and the brain image intensity are not matched, the cerebellar image intensity in the first image is adjusted. The first image is processed through a nonlinear regression to obtain a third image. A neural network identify an infarct region by using the first, second and third images that are cut.

Abstract: A distance measuring device includes a pulsed laser source, a light receiving unit and a computing module. The pulsed laser source emits a laser pulse to a target in accordance with a predetermined period. The light receiving unit has a photon receiving type of light receiving element that receives incident light and outputs a binary pulse, and the binary pulse is used to indicate whether a photon receiving event occurs. The computing module is configured to receive the binary pulse and determine whether an inter-period coincidence event occurs, and the inter-period coincidence event is defined by detecting a plurality of photon receiving events exceeding a predetermined count, on relative positions in a predetermined period number of the predetermined periods. If the calculation module determines that the inter-period coincidence event occurs, a distance of the target is calculated according to time information related to the inter-period coincidence event.

Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.

Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.

Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

Abstract: A handheld radiation image detecting system and an operation method thereof are provided. The handheld radiation image detecting system includes a handheld device including a radiation emitter and a first transceiver and a sensing device including a radiation image sensor and a second transceiver. The first transceiver is coupled to the radiation emitter and used for generating a first wave with directionality. The second transceiver is used for receiving the first wave and for generating a second wave with directionality, and the first transceiver is used for receiving the second wave.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

Abstract: A chip package structure including a first circuit structure, a chip, an electronic device, a first encapsulant, a second encapsulant, a plurality of through pillars, and an electromagnetic interference (EMI) shielding layer is provided. The chip has an active surface facing the first circuit structure. The electronic device has a connection surface facing the first circuit structure. The chip and the electronic device are disposed on opposite sides of the first circuit structure respectively. The first encapsulant encapsulates the chip. The second encapsulant encapsulates the electronic device. The through pillars penetrate the first encapsulant and are electrically connected to the first circuit structure. The EMI shielding layer covers the first encapsulant and the second encapsulant. The chip or the electronic device is grounded by the EMI shielding layer.

Abstract: A handheld radiation image detecting system and an operation method thereof are provided. The handheld radiation image detecting system includes a handheld device including a radiation emitter and a first transceiver and a sensing device including a radiation image sensor and a second transceiver. The first transceiver is coupled to the radiation emitter and used for generating a first wave with directionality. The second transceiver is used for receiving the first wave and for generating a second wave with directionality, and the first transceiver is used for receiving the second wave.

Abstract: According to some aspects of the present disclosure, cooling assemblies for electronic devices are disclosed. Example cooling assemblies include a circuit board having a first surface and a second surface opposite the first surface, a first set of electronic devices, a second set of electronic devices, and a third set of electronic devices. Each set includes at least two electronic devices electrically coupled in parallel and disposed on the first surface of the circuit board. At least one of the electronic devices of the first set is adjacent one of the electronic devices of the second set and is adjacent one of the electronic devices of the third set. The cooling assembly further includes a heat sink disposed on the second surface of the circuit board. The heat sink is in thermal contact with the first set, the second set, and the third set of electronic devices.

Abstract: According to some aspects of the present disclosure, cooling assemblies for electronic devices are disclosed. Example cooling assemblies include a circuit board having a first surface and a second surface opposite the first surface, a first set of electronic devices, a second set of electronic devices, and a third set of electronic devices. Each set includes at least two electronic devices electrically coupled in parallel and disposed on the first surface of the circuit board. At least one of the electronic devices of the first set is adjacent one of the electronic devices of the second set and is adjacent one of the electronic devices of the third set. The cooling assembly further includes a heat sink disposed on the second surface of the circuit board. The heat sink is in thermal contact with the first set, the second set, and the third set of electronic devices.