Abstract: A semiconductor memory structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked over a substrate, and at least an active column disposed over the substrate. The gate layers and the insulating layers are alternately stacked along a first direction. The active column extends along the first direction and penetrates the gate layer and the insulating layer. The active column includes a central portion, a charge-trapping layer surrounding the central portion, and a channel layer between the central portion and the charge-trapping layer. The central portion of the active column includes an isolation structure, a source structure and a drain structure. The source structure and the drain structure are disposed at two sides of the isolation structure.

Abstract: A method includes forming a plurality of memory cells, which includes a plurality of first conductive lines over a substrate, charge-trapping layers coupled to the conductive lines, channel layers arranged adjacent to the charge-trapping layers, and a plurality of first filling regions arranged between the channel layers; etching the first filling regions to form first trenches; depositing a liner over upper surfaces of the charge-trapping layers and the channel layers and sidewalls of the first trenches; forming second filling regions in the first trenches; patterning the second filling regions to form second trenches; depositing a partition region in each of the second trenches; and removing the liner to expose the charge-trapping layers and the channel layers.

Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A first conductive pillar is formed. A plurality of second conductive pillars are formed at different sides of the first conductive pillar. A plurality of dielectric pillars are respectively formed between the first conductive pillar and the plurality of second conductive pillars. A channel layer is formed to continuously surround the first conductive pillar, the plurality of second conductive pillars and the plurality of dielectric pillars. A memory material layer is formed to surround the channel layer.

Abstract: A semiconductor memory device includes a substrate, a stack structure disposed on the substrate, a plurality of dielectric isolation segments extending through the stack structure, and a plurality of memory cell structures. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers alternatingly stacked in a Z direction substantially perpendicular to the substrate. The memory cell structures are disposed in the stack structure, and are separated from one another by the dielectric isolation segments. Each of the memory cell structures includes a pair of conductive segments each penetrating the stack structure in the Z direction, a dielectric separation segment separating the conductive segments, a conductive channel segment enclosing side surfaces of the conductive segments and the dielectric separation segment, and a memory segment enclosing side surface of the conductive channel segment and being connected between the stack structure and the conductive segment.

Abstract: A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (InxSnyTizMmOn). In formula 1, 0<x<1, 0?y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.

Abstract: A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.

Abstract: A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.

Abstract: A memory device includes transistor structures and memory arc wall structures. The memory arc wall structures are embedded in the transistor structures. The transistor structure includes a dielectric column, a source electrode and a drain electrode, a gate electrode layer and a channel wall structure. The source electrode and the drain electrode are located on opposite sides of the dielectric column. The gate electrode layer is around the dielectric column, the source electrode, and the drain electrode. The channel wall structure is extended from the source electrode to the drain electrode and surrounds the dielectric column. The channel wall structure is disposed between the gate electrode layer and the source electrode, between the gate electrode layer, and the drain electrode, and between the gate electrode layer and the dielectric column. The memory arc wall structure is extended on and throughout the channel wall structure.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.