Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

Abstract: A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

Abstract: A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a NAND memory string. The NAND memory string includes a U-shape channel, a first inversion gate electrode and a second inversion gate electrode. The U-shape channel includes a bottom channel surface, a first outer channel sidewall and a second outer channel sidewall. The bottom channel surface is between the first outer channel sidewall and the second outer channel sidewall opposing to the first outer channel sidewall. The first inversion gate electrode is electrically coupled to the U-shape channel and is disposed under bottom channel surface. The second inversion gate electrode is electrically coupled to the U-shape channel and is disposed outside the first outer channel sidewall, and separated from the first inversion gate electrode.

Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.

Abstract: A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction into the substrate from a surface thereof. The multi-layers stack includes a plurality of conductive layers and a plurality of insulating layers alternatively stacked along the first direction on a bottom of the concave portion. The multi-layers stack also has at least one recess passing through the conductive layers and the insulating layers along the first direction, wherein the recess has a cross-sectional bottom profile and a cross-sectional opening profile perpendicular to the first direction and the cross-sectional bottom profile has a size substantially greater than that of the cross-sectional opening profile. The dielectric material is at least partially filled in the recess.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.

Abstract: A stack of sacrificial layers is formed in a set of N levels. A first etch-trim mask having spaced apart first and second open etch regions is formed over the set. Two levels are etched through using the first etch-trim mask in each of M etch-trim cycles, where M is (N?1)/2 when N is odd and (N/2)?1 when N is even. One level is etched through using the first etch-trim mask in one etch-trim cycle when N is even. The first etch-trim mask is trimmed to increase the size of the first and second open etch regions, in each of etch-trim cycles C(i) for i going from 1 to T?1, where T is (N?1)/2 when N is odd and N/2 when N is even. A second etch mask is formed over the set, covering one of the open etch regions. One level is etched through using the second etch mask.

Abstract: A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction into the substrate from a surface thereof. The multi-layers stack includes a plurality of conductive layers and a plurality of insulating layers alternatively stacked along the first direction on a bottom of the concave portion. The multi-layers stack also has at least one recess passing through the conductive layers and the insulating layers along the first direction, wherein the recess has a cross-sectional bottom profile and a cross-sectional opening profile perpendicular to the first direction and the cross-sectional bottom profile has a size substantially greater than that of the cross-sectional opening profile. The dielectric material is at least partially filled in the recess.

Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.

Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a first vertical memory structure, a second vertical memory structure, and an isolation trench. The conductive layers and the insulating layers are interlaced and stacked on the substrate. The first vertical memory structure and the second memory structure penetrate the conductive layers and the insulating layers are formed on the substrate. The first vertical memory structure has a first horizontal C shaped cross-section, and the second vertical memory structure has a second horizontal C shaped cross-section. The isolation trench is formed between the first vertical memory structure and the second vertical memory structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a substrate, conductive layers, insulating layers, a memory structure including first memory structure clusters and second memory structure clusters, isolation trenches, and common source trenches. The conductive layers and the insulating layers are interlaced and stacked on the substrate. Each first memory structure cluster include first memory structures and each first memory structure cluster include second memory structures. The first and second memory structures penetrate the conductive layers and the insulating layers. Each isolation trench is formed between a first memory structure cluster and a second memory structure cluster. The isolation trenches span horizontally on the substrate in a discontinuous manner separated by gaps. Common source trenches are formed on the substrate that run substantially parallel with the isolation trenches.

Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.