Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

Abstract: According to one embodiment, a method of RRAM operations is provided. The method includes the following operations: providing a first voltage difference across a resistor of the RRAM during a read operation; and providing a second voltage difference across the resistor of the RRAM during a reset operation, wherein the first voltage difference has the same polarity as the second voltage difference.

Abstract: A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed.

Abstract: According to another embodiment, a method of reset operation for a resistive random access memory (RRAM) array, having a first RRAM connected to a first word line and a second RRAM connected to a second word line, is provided. A first electrical resistance between the first word line and a word line voltage source is lower than a second electrical resistance between the second word line and the word line voltage source. The method includes: providing a first voltage by using the word line voltage source for resetting the first RRAM; and providing a second voltage by using the word line voltage source for resetting the second RRAM, wherein the first voltage for resetting the first RRAM is lower than the second voltage for resetting the second RRAM.

Abstract: According to another embodiment, a method of a reset operation for a RRAM is provided. The method includes the following operations: providing a first voltage to the dielectric side electrode of the resistor; and providing a second voltage to a gate of the transistor, wherein the first voltage in a second loop is lower than that in a first loop, and the second voltage in the second loop is higher than that in the first loop.

Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

Abstract: A device and method for forming resistive random access memory cell are provided. The method includes: providing a first voltage to a first word line connected to a first RRAM cell to form the first RRAM cell; and providing a negative voltage to a second word line connected to a second RRAM cell that shares a first source line and a first bit line with the first RRAM cell. An exemplary device includes: a first RRAM cell, a second RRAM cell, a first voltage source and a charge pump circuit. The first RRAM cell is connected to a first word line. The second RRAM cell is connected to a second word line. The first voltage source provides a first voltage to the first word line to form the first RRAM cell. The charge pump circuit provides a negative voltage to the second word line.

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.

Abstract: An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree.

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

Abstract: Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data.

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.

Abstract: A two-switch hybrid memory cell device includes a storage node connected between one terminal of a first switch and a gate of a second switch. The device also includes a resistive switching device connected to the storage node. The resistive switching device is to act as a capacitance by being set to a high resistive state when the memory cell is in a dynamic mode.

Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

Abstract: An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree.

Abstract: A method for operating a multi-level resistive random access memory (RRAM) cell having a current-controlling device and a RRAM device connected together. The method is free of a “forming” step and includes setting the RRAM device to one of resistance levels by controlling the current-controlling device to one of current levels. The setting the RRAM device includes applying a first voltage to a top electrode of the RRAM device and applying a second voltage to a bottom electrode of the RRAM device. The second voltage is higher than the first voltage.

Abstract: A memory cell with a decoupled read/write path, the memory cell includes a switch comprising a gate, a first terminal and a second terminal, a resistive switching device connected to the gate of the switch, and a conductive path between the gate of the switch and the second terminal.

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.