Patents by Inventor Yu Wen
Yu Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145511Abstract: An image sensor includes a first sensing unit. The first sensing unit includes a pair of photodiodes formed in a substrate and spaced by a deep trench isolation structure, an outer grid over the pair of photodiodes, a color filter filled in the outer grid, and an inner grid disposed in the color filter. The color filter overlaps the pair of photodiodes. The inner grid includes a first spacer, wherein the first spacer is rotated relative to the deep trench isolation structure.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Jian-Wen LUO, Yu-Chi CHANG, Zong-Ru TU, Po-Hsiang WANG
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Publication number: 20240138326Abstract: A control method for preparing crop nutrient solution, applied in a regulating device, obtains growth data of crops, and determines a growth state of the crops according to the growth data of the crops. The proportion of the nutrient solution required by the crops is determined according to the growth states of the crops, and the culture solution is adjusted according to the proportion of the nutrient solution. After a preset time period, updated growth state of the crops is determined. When the culture solution does not meet the proportion of the nutrient solution corresponding to the updated growth state, the culture solution is adjusted again until the culture solution meet the proportion of the nutrient solution corresponding to the growth state of the crops.Type: ApplicationFiled: March 28, 2023Publication date: May 2, 2024Inventors: YU-SHAN LIN, CHIEN-HAO SU, KAI-SIANG YOU, YAO-WEN TUNG
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Publication number: 20240145380Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
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Publication number: 20240147376Abstract: Apparatus and methods are provided for thermal throttling for UE configured with multi-panel transceiving on FR2. In one novel aspect, the UE prioritizes throttling actions based on signal qualities of each transceiving panel. In one embodiment, the switching to the target panel from the active panel is selected as the highest priority throttling action when the signal quality of the target panel is similar to the active panel. In another embodiment, the UE further determines if the quality of the target panel is sufficient to support mmW transceiving before switching to the target panel. In one embodiment, the UE reduces one or more antennae of an active panel when the signal quality difference between the active panel and the target panel is bigger than a predefined gap threshold.Type: ApplicationFiled: September 22, 2023Publication date: May 2, 2024Inventors: Chih-Chieh Lai, Feng-Wen Weng, Yu-Hung Huang, Chi-Hsiang Lin
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Publication number: 20240143880Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.Type: ApplicationFiled: January 27, 2023Publication date: May 2, 2024Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
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Publication number: 20240139262Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.Type: ApplicationFiled: October 13, 2023Publication date: May 2, 2024Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
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Patent number: 11972975Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.Type: GrantFiled: June 24, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
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Patent number: 11973985Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.Type: GrantFiled: August 22, 2022Date of Patent: April 30, 2024Assignee: MediaTek Inc.Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
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Publication number: 20240135854Abstract: A method involves measuring, for an optical property of the display panel for an input gray level and at a first refresh rate, first and second values at respective first and second ambient brightness levels. The method also involves determining a compensation factor for the input gray level at the first refresh rate. The method further involves determining a modified gamma value at a second refresh rate, wherein the modified gamma value reduces a perceived optical defect of the display panel when operating at the second refresh rate by maintaining a consistent delta difference in values for the optical property between the first and second refresh rates at different ambient brightness levels. The method additionally involves storing the modified gamma value, where the device is configured to adjust input display data using the modified gamma value when transitioning from the first refresh rate to the second refresh rate.Type: ApplicationFiled: April 12, 2021Publication date: April 25, 2024Inventors: Chien-Hui Wen, Hsin-Yu Chen
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Publication number: 20240133421Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.Type: ApplicationFiled: January 17, 2023Publication date: April 25, 2024Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG
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Publication number: 20240133467Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.Type: ApplicationFiled: January 4, 2023Publication date: April 25, 2024Applicant: SUNREX TECHNOLOGY CORP.Inventors: Yu-Xiang GENG, Chun-Chieh CHEN, Ling-Cheng TSENG, Yi-Wen TSAI, Ching-Yao HUANG
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Patent number: 11966077Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.Type: GrantFiled: July 8, 2019Date of Patent: April 23, 2024Assignee: Artilux, Inc.Inventors: Yun-Chung Na, Chien-Lung Chen, Chieh-Ting Lin, Yu-Yi Hsu, Hui-Wen Chen, Bo-Jiun Chen, Shih-Tai Chuang
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Patent number: 11967906Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.Type: GrantFiled: October 11, 2022Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Sheng-Yu Wen, Cheng-Yi Lin, Ting-Yun Lu
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Publication number: 20240128635Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.Type: ApplicationFiled: December 24, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
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Publication number: 20240124163Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.Type: ApplicationFiled: December 19, 2022Publication date: April 18, 2024Applicant: National Cheng Kung UniversityInventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
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Publication number: 20240128341Abstract: The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.Type: ApplicationFiled: December 14, 2022Publication date: April 18, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chia-Hao Chang, Jih-Wen Chou, Hwi-Huang Chen, Hsin-Hong Chen, Yu-Jen Huang
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Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11961768Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.Type: GrantFiled: May 5, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
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Patent number: 11961899Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.Type: GrantFiled: January 23, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen