Abstract: A resonator chip and a manufacturing method thereof are provided. The manufacturing method of the resonator chip includes the following steps. A quartz wafer is provided. The quartz wafer has a first surface and a second surface opposite to the first surface. A first etching process is performed on the quartz wafer to form multiple inverted mesa portions, and the inverted mesa portions has a first thickness. The quartz wafer is singulated to form multiple resonator chips. Each of the resonator chips includes one of the inverted mesa portions. A second etching process is performed on the resonator chips to form chamfers at edges of the resonator chips.

Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Abstract: A lens module includes: a lens barrel including a annular structure, an inner annular surface surrounding the central axis and an outer annular surface opposite to and surrounding the inner annular surface, wherein the inner annular surface forms an accommodating space; an optical lens assembly and an optical filter sequentially disposed in the accommodating space from the object side to the image side; wherein the annular structure is disposed on the inner annular surface and surrounds the central axis, the annular structure includes at least two step portions and at least two bevel portions, all the step portions and the bevel portions are close to the image side, and the optical filter is disposed on the step portions; and the step portions and the bevel portions are alternately disposed along a annular path of the inner annular surface.

Abstract: A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Abstract: A memory structure includes a substrate, a barrier layer, an etch stop layer, a bottom electrode, a data storage feature and a top electrode. The substrate has a metal trench. The barrier layer is disposed over the metal trench. The etch stop layer surrounds the barrier layer, and, together with the barrier layer, completely covers the metal trench. The bottom electrode is disposed over the barrier layer. The data storage feature is disposed over the bottom electrode. The top electrode is disposed over the data storage feature.

Abstract: A method and apparatus of signal processing using a grouped neural network (NN) process are disclosed. A plurality of input signals for a current layer of NN process are grouped into multiple input groups comprising a first input group and a second input group. The neural network process for the current layer is partitioned into multiple NN processes comprising a first NN process and a second NN process. The first NN process and the second NN process are applied to the first input group and the second input group to generate a first output group and a second output group for the current layer of NN process respectively. In another method, the parameter set associated with a layer of NN process is coded using different code types.

Abstract: A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coder receives a set of transform coefficients of the current block. The video coder identifies multiple transform hypotheses. Each hypothesis includes two or more predicted transform parameters. The video coder computes a cost for each hypothesis by performing inverse transform on the transform coefficients of the current block according to the predicted transform parameters of the hypothesis. The video coder signals or receives a codeword that identifies a first transform mode of a first transform parameter. The codeword is assigned to the first transform mode based on the calculated costs of the multiple transform hypotheses. The video coder encodes or decodes the current block by reconstructing the current block according to the identified first transform mode.

Abstract: A method for signaling arbitrary partition boundaries is provided. A video coder derives a partitioning structure for splitting the current block by identifying a partitioning position having a lowest cost. The video coder splits the current block into first and second partitions according to the identified partitioning position. The video coder encodes or decodes the first and second partitions of the current block. The first and second partitions may be associated with first and second templates that are constructed based on reconstructed pixels neighboring the current block. The video coder may identify the partitioning position by computing a first cost based on the first template and a second cost based on the second template and optimizing the partitioning position to minimize a sum of the first and second costs.

Abstract: Conventional intra-prediction uses pixels from left and upper neighbour blocks to predict a macroblock (MB). Thus, the MBs must be sequentially processed, since reconstructed left and upper MBs must be available for prediction. In an improved method for encoding Intra predicted MBs, a MB is encoded in two steps: first, a first portion of the MB is encoded independently, without references outside the MB. Pixels of the first portion can be Intra predicted using DC mode. Then, the first portion is reconstructed. The remaining pixels of the MB, being a second portion, are intra predicted from the reconstructed pixels of the first portion and then reconstructed. The first portion comprises at least one column or one row of pixels of the MB. The encoding is applied to at least two Intra predicted MBs per slice, or per picture if no slices are used.

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

Abstract: A method for designing an integrated circuit comprises identifying a first circuit component that presents a voltage (IR) drop being equal to or greater than an IR drop threshold through at least an IR drop analysis, splitting the plurality of timing paths into a first subset of timing paths and a second subset of timing paths, based on a timing margin threshold; and adding a second circuit component disposed along the second subset of timing paths, while keeping the first circuit component disposed along the first subset of timing paths. The first circuit component can be disposed along a plurality of timing paths that each extend from a first storage node and to a second storage node and can be each associated with a timing margin.

Abstract: A video coding system that reorders prediction candidates is provided. A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coder identifies possible candidate prediction positions. The video coder computes a cost for each of the identified possible candidate prediction positions. The video coder assigns, based on the computed costs, a reordered index to each of N lowest cost candidate prediction positions from the identified possible candidate prediction positions. The video coder selects a candidate prediction position using the assigned reordered indices, wherein the selection is signaled in or parsed from the bitstream. The video coder encodes or decodes the current block by using the selected candidate prediction position.

Abstract: The disclosure discloses a noise reduction headphone, a noise reduction method and apparatus, a storage medium and a processor. The noise reduction headphone includes: a first noise reduction channel, wherein the first noise reduction channel at least includes: at least one first feed-forward microphone, at least one feed-back microphone, a first feed-forward noise reduction processing unit, a feed-back noise reduction processing unit, and a first loudspeaker; and a second noise reduction channel, wherein the second noise reduction channel at least includes: at least one second feed-forward microphone, a second feed-forward noise reduction processing unit, and a second loudspeaker; wherein the first feed-forward noise reduction processing unit and the second feed-forward noise reduction processing unit are configured to process ambient noise signals, the feed-back noise reduction processing unit is configured to process an ear canal noise signal.

Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Abstract: An integrated circuit structure includes a plurality of transistors, an interconnect layer, and a memory stack. The interconnect layer includes an interlayer dielectric (ILD) and a conductive structure embedded in the ILD. The conductive structure includes a barrier layer and a conductive filling material surrounded by the barrier layer in a cross-sectional view. The memory stack is over the interconnect layer. The memory stack includes a bottom electrode extending across the conductive structure in the cross-sectional view, a resistance switching layer over the bottom electrode, and a top electrode over the resistance switching layer. In the cross-sectional view, an interface formed by the bottom electrode and the barrier layer has a topmost point higher than a topmost point of an interface formed by the bottom electrode and the conductive filling material.

Abstract: A method for video decoding includes receiving a video frame reconstructed based on data received from a bitstream. The method further includes extracting, from the bitstream, a first syntax element indicating whether a spatial partition for partitioning the video frame is active. The method also includes, responsive to the first syntax element indicating that the spatial partition for partitioning the video frame is active, determining a configuration of the spatial partition for partitioning the video frame, determining a plurality of parameter sets of a neural network, and applying the neural network to the video frame. The video frame is spatially divided based on the determined configuration of the spatial partition for partitioning the video frame into a plurality of portions, and the neural network is applied to the plurality of portions in accordance with the determined plurality of parameter sets.

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.