Abstract: The disclosure discloses a noise reduction headphone, a noise reduction method and apparatus, a storage medium and a processor. The noise reduction headphone includes: a first noise reduction channel, wherein the first noise reduction channel at least includes: at least one first feed-forward microphone, at least one feed-back microphone, a first feed-forward noise reduction processing unit, a feed-back noise reduction processing unit, and a first loudspeaker; and a second noise reduction channel, wherein the second noise reduction channel at least includes: at least one second feed-forward microphone, a second feed-forward noise reduction processing unit, and a second loudspeaker; wherein the first feed-forward noise reduction processing unit and the second feed-forward noise reduction processing unit are configured to process ambient noise signals, the feed-back noise reduction processing unit is configured to process an ear canal noise signal.

Abstract: A video coding system that reorders prediction candidates is provided. A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coder identifies possible candidate prediction positions. The video coder computes a cost for each of the identified possible candidate prediction positions. The video coder assigns, based on the computed costs, a reordered index to each of N lowest cost candidate prediction positions from the identified possible candidate prediction positions. The video coder selects a candidate prediction position using the assigned reordered indices, wherein the selection is signaled in or parsed from the bitstream. The video coder encodes or decodes the current block by using the selected candidate prediction position.

Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Abstract: An integrated circuit structure includes a plurality of transistors, an interconnect layer, and a memory stack. The interconnect layer includes an interlayer dielectric (ILD) and a conductive structure embedded in the ILD. The conductive structure includes a barrier layer and a conductive filling material surrounded by the barrier layer in a cross-sectional view. The memory stack is over the interconnect layer. The memory stack includes a bottom electrode extending across the conductive structure in the cross-sectional view, a resistance switching layer over the bottom electrode, and a top electrode over the resistance switching layer. In the cross-sectional view, an interface formed by the bottom electrode and the barrier layer has a topmost point higher than a topmost point of an interface formed by the bottom electrode and the conductive filling material.

Abstract: A method for video decoding includes receiving a video frame reconstructed based on data received from a bitstream. The method further includes extracting, from the bitstream, a first syntax element indicating whether a spatial partition for partitioning the video frame is active. The method also includes, responsive to the first syntax element indicating that the spatial partition for partitioning the video frame is active, determining a configuration of the spatial partition for partitioning the video frame, determining a plurality of parameter sets of a neural network, and applying the neural network to the video frame. The video frame is spatially divided based on the determined configuration of the spatial partition for partitioning the video frame into a plurality of portions, and the neural network is applied to the plurality of portions in accordance with the determined plurality of parameter sets.

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.

Abstract: Examples of an engineered knitted garment with a number of integrated compression zones are disclosed. The engineered knitted garment may be a pair of tights having a first compression zone located at the calves, a second compression zone located at the knees, and a third compression zone located at the waist. The compressive moduli of the compression zones may be different to provide higher compression in areas where greater support is required (e.g., at the calves) and lower compression in areas where greater mobility is required (e.g., at the knees).

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.

Abstract: A spatial light modulator device includes an array of spatial light modulator cells located over a substrate. Each of the spatial light modulator cells includes: a layer stack including a phase change material plate, a spacer dielectric material plate that underlies the phase change material plate, and a metallic heater plate underlying the spacer dielectric material plate and including outer sidewalls; and a pair of bottom electrode via structures contacting a respective surface segment of a bottom surface of the metallic heater plate. Each of the outer sidewalls of the metallic heater plate is vertically coincident with a respective sidewall of the spacer dielectric material plate and with a respective sidewall of the phase change material plate.

Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.

Abstract: Disclosed is an electronic device including a display module, a touch light-emitting module, and a processing unit. The touch light-emitting module includes a light-transmitting unit, a touch unit, and a light-emitting unit. The touch unit is disposed under the light-transmitting unit and is adapted to generate a touch signal based on touch of the user on the light-transmitting unit. The light-emitting unit is disposed on the touch unit. The light-emitting unit is adapted to provide an illumination beam to the light-transmitting unit according to an illumination signal. The processing unit is electrically connected to the display module and the touch light-emitting module. When the electronic device is switched to a touch mode, the processing unit disables the light-10 emitting unit. When the electronic device is switched to a content input mode, the processing unit enables the light-emitting unit to provide the illumination beam to the light-transmitting unit.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.

Abstract: A method and apparatus for video coding are disclosed. According to the method, a set of MC (Motion Compensation) candidates with each MC candidate comprising predicted samples for coding boundary pixels of the current block are determined. The set of MC candidates comprises a first candidate, and wherein the first candidate corresponds to a weighted sum of first predicted pixels generated according to first motion information of the current block and second predicted pixels generated according to second motion information of a neighbouring boundary block of the current block. Boundary matching costs associated with the set of MC candidates are determined respectively. A final candidate is determined from the set of MC candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.

Abstract: A method for manufacturing a semiconductor device includes: forming an etch stop layer with an opening; forming a barrier layer on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion to be inserted into the opening of the etch stop layer; forming a bottom electrode layer on the layer portion of the barrier layer opposite to the etch stop layer; forming a ferroelectric layer on the bottom electrode layer opposite to the barrier layer; and forming a top electrode layer on the ferroelectric layer opposite to the bottom electrode layer.

Abstract: A power converter includes an input circuit, a conversion circuit, an output circuit and a processor. The input circuit is configured to receive and detect a front stage power from a front stage device. The conversion circuit is coupled to the input circuit. The output circuit is coupled to the conversion circuit and configured to supply power to a back stage device. The processor is coupled to the input circuit, the conversion circuit and the output circuit. The processor is configured to determine whether the front stage power is stable, and is configured to handshake with the back stage device to confirm a conversion power agreed by the back stage device. The processor is further configured to control the conversion circuit to operate at the conversion power, so as to generate an output power to the back stage device.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.