Patents by Inventor Yu Wen

Yu Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240357083
    Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for a current block is determined, where the current template includes an inside current template including inside prediction samples or inside partially reconstructed samples inside the current block. The inside partially reconstructed samples are derived by adding a DC value of the current block to the inside prediction samples. Corresponding candidate reference templates associated with the current block are determined at a set of candidate locations. A location of a target reference template among the candidate reference templates that achieves a best match between the current template and the candidate reference templates is determined. An initial motion vector (MV) is then refined according to the location of the target reference template.
    Type: Application
    Filed: August 12, 2022
    Publication date: October 24, 2024
    Inventors: Olena CHUBACH, Chun-Chia CHEN, Man-Shu CHIANG, Tzu-Der CHUANG, Ching-Yeh CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20240357153
    Abstract: Method and apparatus for template matching with a determined area are disclosed. According to this method, a current template comprising current neighbouring pixels on an above side of the current block, on a left side of the current block, or a combination thereof for a current block is received. An area in a reference picture is then determined, where the reference picture corresponds to a previously coded picture. A matching result between a restricted reference template of a reference block and the current template is then determined, wherein the restricted reference template is generating by using only neighbouring reference pixels of a reference template inside the determined area, the reference template has a same shape as the current template, and a location of the reference template is determined according to a target motion vector (MV) from the current template.
    Type: Application
    Filed: August 18, 2022
    Publication date: October 24, 2024
    Inventors: Chun-Chia CHEN, Olena CHUBACH, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20240357081
    Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, input data associated with a current block of a video unit in a current picture are received. Motion compensation is then applied to the current block according to an initial motion vector (MV) to obtain initial motion-compensated predictors of the current. After applying the motion compensation to the current block, template-matching MV refinement is applied to the current block to obtain a refined MV for the current block. The current block is then encoded or decoded using information including the refined MV. The method may further comprise determining gradient values of the initial motion-compensated predictors. The initial motion-compensated predictors can be adjusted by taking into consideration of the gradient values and/or MV difference between the refined and initial MVs.
    Type: Application
    Filed: August 18, 2022
    Publication date: October 24, 2024
    Inventors: Chun-Chia CHEN, Olena CHUBACH, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 12126945
    Abstract: A focus identification method adaptable for a focus identification system is provided. The focus identification method includes: capturing a projection picture to generate a captured picture; dividing the captured picture into a plurality of image regions; calculating a plurality of sharpness values corresponding to the plurality of image regions respectively according to image data of the plurality of image regions; and displaying the plurality of sharpness values on the projection picture corresponding to the plurality of image regions respectively the to generate a first focus identification picture. Moreover, the disclosure further discloses a focus identification system applying the focus identification method. The focus identification method and the focus identification system using the same in the disclosure may improve the remote maintenance efficiency.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: October 22, 2024
    Assignee: Coretronic Corporation
    Inventors: Yu-Wen Lo, Chien-Chun Peng
  • Publication number: 20240345211
    Abstract: An electronic device and a control method thereof are provided. The electronic device includes a DSP (Digital Signal Processor). The DSP receives a digital signal. The digital signal includes a plurality of frames. The DSP divides the plurality of frames into a vital group and a non-vital group according to a criterion. The DSP compares a total number of frames of the vital group with a threshold value. In response to the total number of frames of the vital group being greater than the threshold value, the DSP may calculate signal strength of the vital group.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 17, 2024
    Inventors: Chuan Yen KAO, Yu Wen HUANG, Wei Rong TSENG, Yao Tsung CHANG, Yin Yu CHEN
  • Publication number: 20240347626
    Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Inventors: TSUNG-HUA YANG, CHENG-BO SHU, CHIA-TA HSIEH, PING-CHENG LI, PO-WEI LIU, SHIH-JUNG TU, TSUNG-YU YANG, YUN-CHI WU, YU-WEN TSENG
  • Patent number: 12120293
    Abstract: A video coding system generating candidates for Merge Mode with Motion Vector Difference (MMVD) with reduced resource usage is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies multiple MMVD candidates for different offset positions based on a merge candidate of the current block. The system generates reference samples for the identified MMVD candidates. The system reconstructs the current block or encodes the current block into a bitstream by using the generated reference samples. The system processes the MMVD candidates in separate groups: a first group of vertical MMVD candidates and a second group of horizontal MMVD candidates. The system generates the reference samples for the identified MMVD candidates by applying a vertical filter to source reference samples of horizontal MMVD candidates and then applying a horizontal filter to outputs of the vertical filter.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: October 15, 2024
    Assignee: MediaTek Inc.
    Inventors: Cheng-Yen Chuang, Man-Shu Chiang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240332076
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 12105355
    Abstract: A wide-angle lens assembly includes a first lens, a second lens, a third lens, a fourth lens, and a fifth lens. The first lens is a meniscus lens with refractive power and includes a convex surface facing an object side and a concave surface facing an image side. The second lens is with refractive power. The third lens is with positive refractive power. The fourth lens is with refractive power. The fifth lens is with positive refractive power and includes a convex surface facing the image side. The first lens, the second lens, the third lens, the fourth lens, and the fifth lens are arranged in order from the object side to the image side along an optical axis.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: October 1, 2024
    Assignees: Sintai Optical (Shenzhen) Co., Ltd., Asia Optical Co., Inc.
    Inventors: Chia-Hung Sun, Tsan-Haw Lee, Yu-Wen Tai, Shu-Hung Lin
  • Publication number: 20240315435
    Abstract: A handle includes a handle member, two fixing mechanisms, and two fixing mechanisms. The handle member includes a gripping portion and two extending portions connected to two ends of the gripping portion. The gripping portion extends along a first direction, each extending portion extends from the gripping portion along a second direction. The two fixing mechanisms are spaced apart from each other and can connect to a product. Each linkage mechanism is connected between one extending portion and one fixing mechanism. Each linkage mechanism includes a first connecting member and a second connecting member connected to each other. Each first connecting member is rotatably connected to each fixing mechanism. Each second connecting member is telescopically connected to each extending portion along the second direction. The present application further provides a circuit board assembly and an electronic device.
    Type: Application
    Filed: August 28, 2023
    Publication date: September 26, 2024
    Inventor: YU-WEN CHANG
  • Patent number: 12100592
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Yong-Jin Liou, Yu-Wen Chen, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
  • Patent number: 12099078
    Abstract: A probe card and a wafer testing assembly thereof are provided. The wafer testing assembly includes a printed circuit board, a space transformer, a plurality of copper pillars and a plurality of strengthening structure units. The printed circuit board includes a bottom surface and a plurality of first contacts arranged on the bottom surface. The space transformer includes a top surface and a plurality of second contacts. The second contacts are arranged on the top surface and corresponding to the first contacts. The copper pillars are respectively arranged between the first contacts and the second contacts. Two ends of each of the copper pillars are respectively electrically connected to the first contacts and the second contacts. The strengthening structure units are arranged on the bottom surface of the printed circuit board and respectively surrounding the copper pillars.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: September 24, 2024
    Assignee: MPI CORPORATION
    Inventors: Yi-Chien Tsai, Huo-Kang Hsu, Yu-Wen Chou, Yu-Shan Hu
  • Patent number: 12096657
    Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: September 17, 2024
    Assignee: Apple Inc.
    Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
  • Patent number: 12093510
    Abstract: The present disclosure provides a method and electronic apparatus for modifying pages of an electronic document, and the method is performed by the electronic apparatus and comprises the following steps: opening a first user operation interface; detecting whether a first input region is selected; when it is detected that the first input region is selected, displaying a plurality of first pages of a first electronic document on a page preview region and determining a first page change position located in the plurality of first pages according to a first operation event; detecting whether a second input region is selected; when it is detected that the second input region is selected, displaying a plurality of second pages of a second electronic document on the page preview region and determining at least one second page of the plurality of second pages according to a second operation event; and adding the at least one second page to the first page change position according to a third operation event.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: September 17, 2024
    Assignee: KDAN MOBILE SOFTWARE LTD.
    Inventors: Yu-Wen Chen, Kai-Lin Shih
  • Patent number: 12095993
    Abstract: A method and apparatus for video coding using a coding mode belonging to a mode group comprising an Intra Block Copy (IBC) mode and an Intra mode are disclosed. According to the present invention, for both IBC and Intra mode, a same default scaling matrix is used to derive the scaling matrix for a current block. In another embodiment, for the current block with block size of M×N or N×M, and M greater than N, a target scaling matrix is derived from an M×M scaling matrix by down-sampling the M×M scaling matrix to an M×N or N×M scaling matrix.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 17, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chen-Yen Lai, Olena Chubach, Tzu-Der Chuang, Ching-Yeh Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Publication number: 20240291985
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system. A method receives input data associated with a current block in a current picture, determines if the current block is an out-of-bounds node, wherein the out-of-bounds node is a coding tree node of the current picture with a block region across a current picture boundary, and determines whether the current block is larger than a predefined size. The method further determines an inferred splitting type if the current block is an out-of-bounds node and the current block is larger than the predefined size and applies the inferred splitting type to split the current block into child blocks if the current block is an out-of-bounds node and the current block is larger than the predefined size, and then adaptively splitting each child block into one or more leaf blocks.
    Type: Application
    Filed: May 9, 2024
    Publication date: August 29, 2024
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG, Shih-Ta HSIANG
  • Patent number: 12075634
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20240276951
    Abstract: A combined brush and comb contains a body, a fixing cushion, multiple bristle sets, and multiple spherical needles. The fixing cushion is disposed on the body and includes multiple receiving notches and multiple through orifices. A respective one receiving notch includes an opening defined on a top thereof, and the respective one receiving notch includes a bottom face formed on a bottom thereof. A diameter of the respective one receiving notch increases from the opening to the bottom face. The multiple bristle sets are fixed in the multiple receiving notches. The multiple spherical needles are mounted in the multiple through orifices. A respective one spherical needle includes an inverted H-shaped base, and the inverted H-shaped base has a first engagement section, a second engagement extension parallel to and spaced from the first engagement extension, and a trench defined between the first engagement extension and the second engagement extension.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventor: Yu Wen Liao
  • Publication number: 20240276897
    Abstract: A phase-change material switch may include a first interconnect-level dielectric, a heat spreader formed within the first interconnect-level dielectric, a second interconnect-level dielectric formed over the heat spreader, a phase change material element formed in or over the second interconnect-level dielectric, a first electrode and a second electrode in electrically conductive contact with the phase change material element, and a heating element coupled to the phase change material element and configured to supply a heat pulse to the phase change material element. The heat spreader may be located proximate to a first one of the phase change material element and the heating element, and the heat spreader may be smaller than the phase change material element. The heat spreader may be form using materials and processes similar to those used to form electrical interconnects, but unlike electrical interconnects, the heat spreader may be electrically isolated from electrical interconnects.
    Type: Application
    Filed: February 15, 2023
    Publication date: August 15, 2024
    Inventors: Han-Yu CHEN, Chang-Chih HUANG, Yu-Wen WANG, Yi-Han CHENG, Kuo-Chyuan TZENG
  • Patent number: D1042992
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: September 17, 2024
    Inventor: Yu Wen