Patents by Inventor Yu Wen Cheng

Yu Wen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200317506
    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • Publication number: 20200274113
    Abstract: Vertical via connections to a battery are hermetically sealed to prevent environmental factors (e.g. moisture, oxygen, and nitrogen) from entering the internals of the battery through porous conductive material filling the vias resulting in reduced battery performance and battery failure.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Inventors: Bing Dang, Qianwen Chen, Yu Luo, John Knickerbocker, Jae-Woong Nah, Kai Liu, Po-wen Cheng, Tung-hsiu Shih, Mengnian Niu, Kai-wei Nieh
  • Patent number: 10752497
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a plurality of interconnect layers disposed within a dielectric structure over a substrate. A passivation layer is over the dielectric structure. A sensing electrode and a bonding electrode have bottom surfaces directly contacting the passivation layer. A microelectromechanical systems (MEMS) substrate is vertically separated from the sensing electrode. The bonding electrode is electrically connected to the MEMs substrate and to one or more of the plurality of interconnect layers. An electrode extension via is configured to electrically connect the sensing electrode to one or more of the plurality of interconnect layers.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
  • Patent number: 10748940
    Abstract: A TFT substrate for a touch display panel of reduced thickness defines a display area and a surrounding non-display area. The TFT substrate includes a first conductive layer on the substrate and a second conductive layer on the first conductive layer. In the display area, the first conductive layer includes data lines and the second conductive layer includes common electrodes. Each common electrode extends as a strip along a first direction. Each data line extends along a second direction. The first direction intersects the second direction. Each data line crosses the common electrodes. Each data line functions as a touch driving electrode and each common electrode functions as a touch sensing electrode.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 18, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chia-Lin Liu, Yu-Fu Weng, Chien-Wen Lin, Tzu-Yu Cheng
  • Patent number: 10734325
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Long-Yi Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen, Yu-Ching Wang, Po-Chung Cheng, Hsin-Chin Lin, Meng-Wei Chen, Kuei-Shun Chen
  • Patent number: 10689247
    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 10690950
    Abstract: A touch display device includes a touch display module. The touch display module includes a TFT substrate, a color filtering substrate, and a liquid crystal layer encapsulated between the TFT substrate and the color filtering substrate. A first electrode layer is formed on a surface of the color filtering substrate facing the TFT substrate. A second electrode layer is formed on a surface of the TFT substrate facing the color filtering substrate. The touch display device further includes at least one supporting element on a side of the touch display module. The supporting element is elastic and configured for elastically resisting against the touch display module.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 23, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu, Tzu-Yu Cheng
  • Patent number: 10656744
    Abstract: A thin film transistor array substrate in a touch display panel having reinforced common voltage uniformity on sub-electrodes therein includes a common electrode layer, a driving circuit, a controlling switch, a plurality of first lines, at least one second line, and at least one third line. The common electrode layer includes the spaced sub-electrodes. Each sub-electrode uses a first line electrically connect to the driving circuit and the controlling switch. The at least one second line is electrically connected to the driving circuit and the controlling switch, and when the controlling switch is turned on, the second line is electrically connected to the first lines, the driving circuit thus applying a common voltage to the sub-electrodes. A touch display panel using the thin film transistor array substrate is also provided.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 19, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu, Tzu-Yu Cheng
  • Publication number: 20200152763
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 10642395
    Abstract: A shift register driving a touch display device generates shifted pulse signals shifted by a specified phase. The shift register includes unit circuits connected in multiple stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor is controlled by a first control signal and outputs a high-level voltage to a first node based on the value of a trigger signal. The output transistor outputs the shifted pulse signal, which is synchronous with a clock control signal, based on the value of the high-level voltage of the first node. A blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit. After the blank period, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 5, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Tzu-Yu Cheng
  • Publication number: 20200135617
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.
    Type: Application
    Filed: April 23, 2019
    Publication date: April 30, 2020
    Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
  • Publication number: 20200111739
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20200058595
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Yi CHEN, Jia-Hong CHU, Chi-Wen LAI, Chia-Ching LIANG, Kai-Hsiung CHEN, Yu-Ching WANG, Po-Chung CHENG, Hsin-Chin LIN, Meng-Wei CHEN, Kuei-Shun CHEN
  • Publication number: 20200056841
    Abstract: The present invention is related to an UV LED curing apparatus, and more particularly, to an UV LED curing apparatus with improved housing and switch controller. The light reflective inner casing is preferably provided as an effective UV light reflector and as a supporting substrate of the UV LED light source while being capable of transmitting heat from the UV LED light source away for further heat dissipation to the ambient by the outer casing. The outer casing is detachably attached to the inner casing and allows a greater user interaction for decorative and entertainment purposes while also being a protective and heat dissipation means.
    Type: Application
    Filed: September 9, 2019
    Publication date: February 20, 2020
    Inventors: Danny Lee Haile, Kuo-Chang Cheng, Yu-Jen Li, Ya-Wen Wu, Pei-Chen Yang
  • Publication number: 20200051858
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Patent number: 10535748
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Publication number: 20200012368
    Abstract: A shift register driving a touch display device generates shifted pulse signals shifted by a specified phase. The shift register includes unit circuits connected in multiple stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor is controlled by a first control signal and outputs a high-level voltage to a first node based on the value of a trigger signal. The output transistor outputs the shifted pulse signal, which is synchronous with a clock control signal, based on the value of the high-level voltage of the first node. A blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit. After the blank period, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 9, 2020
    Inventors: YU-FU WENG, CHIEN-WEN LIN, TZU-YU CHENG
  • Patent number: 10529081
    Abstract: A depth image processing method and a depth image processing system are provided. The depth image processing method includes: capturing a first image and a second image; performing a feature comparison to acquire a plurality of feature pairs between the first image and the second image, wherein each of the feature pairs includes a feature in the first image and a corresponding feature in the second image; computing disparities of the feature pairs; computing a depth image through the first image and the second image when the disparities of the feature pairs are all smaller than a disparity threshold.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignee: Wistron Corporation
    Inventors: Sheng-Shien Hsieh, Kai-Chung Cheng, Yu-Wen Huang, Tzu-Yao Lin, Pin-Hong Liou
  • Publication number: 20200004366
    Abstract: A touch display panel which includes an integral fingerprint recognition portion also comprises a central processor, a switch module, and a main touch portion. The fingerprint recognition portion comprises fingerprint recognition electrodes connected to the central processor. The main touch portion comprises touch electrodes to sense touches. At least one touch electrode is electrically connected to one fingerprint recognition electrode through the switch module, and the switch module is controlled by the processor to cycle through connected or disconnected states between the touch electrode and the fingerprint recognition electrode.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: YU-FU WENG, CHIEN-WEN LIN, CHIA-LIN LIU, TZU-YU CHENG
  • Publication number: 20190391440
    Abstract: A touch display device includes a touch display module. The touch display module includes a TFT substrate, a color filtering substrate, and a liquid crystal layer encapsulated between the TFT substrate and the color filtering substrate. A first electrode layer is formed on a surface of the color filtering substrate facing the TFT substrate. A second electrode layer is formed on a surface of the TFT substrate facing the color filtering substrate. The touch display device further includes at least one supporting element on a side of the touch display module. The supporting element is elastic and configured for elastically resisting against the touch display module.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 26, 2019
    Inventors: YU-FU WENG, CHIEN-WEN LIN, CHIA-LIN LIU, TZU-YU CHENG