Abstract: Techniques for managing network-accessible infrastructure metadata are provided. A method includes receiving a resource request comprising resource metadata corresponding to a network-accessible infrastructure resource, determining whether to commit the resource request based at least in part on a constraint associated with the network-accessible infrastructure resource, and, in accordance with a determination to commit the resource request: generating, by the computer system, a resource identifier describing resource metadata in accordance with the resource request, storing, by the computer system, the resource metadata in a data store in communication with the computer system, receiving, by the computer system, a data request to provide the resource metadata described by the resource identifier, and providing, by the computer system, the resource metadata described by the resource identifier in accordance with the data request.

Abstract: The present invention discloses a port district sea line multiple vessel monitoring system and operating method thereof. Specifically, the port district sea line multiple vessel monitoring system comprises a processing module, a storage module, a camera and a floating object information receiving module. The port district sea line multiple vessel monitoring system may automatically recognize image classification of water surface object, therefore to determine operation of patrol mode, monitor mode or auxiliary recognizing mode for satisfying the needs of monitoring of port district sea line.

Abstract: An apparatus and a system are provided. The system includes a top plate electrode, a dielectric layer, a plurality of pixel electrode circuits, and a plurality of detection circuits. A droplet is disposed between the top plate electrode and the dielectric layer. The plurality of pixel electrode circuits are arranged in a two-dimensional array. The pixel electrode circuits in each column of the two-dimensional array are electrically connected to a respective detection circuit of the plurality of detection circuits.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

Abstract: Disclosed are a peptide compound and an application thereof, and a composition containing the peptide compound. The present invention provides a peptide compound YA-156, and a pharmaceutically acceptable salt, a tautomer, a solvate, a crystal form or a prodrug thereof. The compound has good stability and good activity for Kiss1R.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

Abstract: A composite intermediary device using vertical probe for wafer testing, comprising: a printed circuit board, a glass interposer and a vertical probe set; wherein the printed circuit board has printed circuit connected with a measuring apparatus, the glass interposer has multiple contact pads connected with the printed circuit, and then the probes of the vertical probe set are against the contact pads of the glass interposer and the bumps of the device under test. By a fine pitch configuration of the printed circuit and the contact pads of the glass interposer, the present invention achieves the requirements of synchronous and interleaved testing of multiple ICs.

Abstract: Monolithic power stage (Pstage) packages and methods for using same are provided that may be implemented to provide lower thermal resistance/enhanced thermal performance, reduced noise, and/or smaller package footprint than conventional monolithic Pstage packages. The conductive pads of the disclosed Pstage packages may be provided with a larger surface area for contacting respective conductive layers of a mated PCB to provide a more effective and increased heat transfer away from a monolithic Pstage package. In one example, the increased heat transfer away from the monolithic Pstage package results in lower monolithic Pstage package operating temperature and increased power output.

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A boot control circuit of a computer system is provided. The boot control circuit is coupled to a system power module. The boot control circuit includes a connection port module and a motherboard. The connection port module includes a detection pin. The motherboard includes a switch for controlling the system power module. The motherboard controls the system power module to provide power for booting the computer system according to a connection between the detection pin and the switch.

Abstract: An electromagnetic wave absorption structure includes at least two electromagnetic wave composite absorbing layers stacked and overlapped with each other. Each of the electromagnetic wave composite absorbing layers comprises a conductive composite layer and an insulating layer, and the insulating layer is stacked and overlapped with the conductive composite layer. The conductive composite layer comprises a plurality of conductive layers and a plurality of interlayer insulating layers, and the conductive layers and the interlayer insulating layers are stacked in a staggered manner. The ratio of a thickness of one of the plurality of insulating layers to a thickness of one of the plurality of interlayer insulating layers is greater than or equal to 20.

Abstract: Described herein are systems, methods, and software to manage multi-type storage in a cluster computing environment. In one example, a host can identify health and performance information at a first time for each local data store on the host and a hyperconverged data store available to the host. The host can further identify health and performance information associated with the data stores at a second time and can compare the health and performance information at the first time and the second time to identify differences in the information. The host then communicates the differences to a second host in the computing environment.

Abstract: A shoelace is provided, including: a core material and a woven layer. The core material defines an axial direction, and the woven layer is sleeved on the core material. The woven layer includes a plurality of strands, a plurality of ridge portions and a plurality of connecting portions. The plurality of ridge portions and the plurality of connecting portions are woven by the plurality of strands and arranged alternatively in a circumferential direction of the core material.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: An access control list (ACL) management method is provided. The ACL management method is used in a file system and includes: storing an ACL pattern, where the ACL pattern corresponds to a subtree of a directory tree in the file system and includes a root access control list (RACL), the ACL of the root node of the subtree is the RACL, the ACL of each non-root directory of the subtree is the same inherited directory access control list (DACL) generated according to the RACL, and the ACL of each non-root file of the subtree is the same inherited file access control list (FACL) generated according to the RACL. A data storage device and a computer-readable medium for executing the ACL management method are also provided.

Abstract: A display panel and a driving method thereof are provided. The driving method includes: acquiring a display synchronization signal, and according to it to determine a first backlight synchronization signal including a plurality of second pulses corresponding to a plurality of first pulses in the display synchronization signal; acquiring a display setting frequency greater than a minimum value of refresh rates of frame images, and according to it to determine a unit backlight clock signal, where a duration of the unit backlight clock signal is equal to of a reciprocal of the display setting frequency; and generating a third pulse between some two adjacent second pulses to drive a backlight plate to emit light.

Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.