Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Abstract: A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.

Abstract: A driving assistance system and a driving assistance method are provided. The driving assistance system includes a plurality of image capturing devices, a congestion calculation module, and a determination module. The image capturing devices capture a plurality of regional images of a plurality of road sections of the target lane. The congestion calculation module calculates a plurality of congestion levels corresponding to the road sections according to the regional images. The determination module provides a lane changing message to the vehicle according to the congestion levels.

Abstract: System and method for testing power conversion devices are provided. A power supply grid is connected to an AC terminal of a first power conversion device, the power supply grid is also connected to an AC terminal of the second power conversion device, and a DC terminal of the first power conversion device is connected to a DC terminal of the second power conversion device. In this way, a test loop is formed by the power supply grid, the first power conversion device and the second power conversion device. In this test loop, the first power conversion device and the second power conversion device act as a load and a power source, so no additional DC power supply and load are required during the test.

Abstract: A silicone hydrogel composition includes a first hydrophilic monomer, a siloxane compound, a first crosslinking monomer, a second hydrophilic monomer, and a second crosslinking monomer. The first hydrophilic monomer and the siloxane compound have an acrylate group or an acrylamide group and may also have a methacrylate group or a methacrylamide group. The first crosslinking monomer has a plurality of acrylate groups or acrylamide groups and may also have methacrylate groups or methacrylamide groups. The second hydrophilic monomer has a non-conjugated vinyl group. The second crosslinking monomer has a plurality of non-conjugated vinyl groups. A sum of the weights of the second hydrophilic monomer and the second crosslinking monomer is 40 to 100 parts by weight, relative to 100 parts by weight of the sum of the weights of the first hydrophilic monomer, the siloxane compound, and the first crosslinking monomer.

Abstract: An additive manufacturing process for forming a metallic layer on the surface of the substrate includes fabricating a substrate from a polymerizable composition by a stereolithographic process, and contacting the reactive surface with an aqueous solution including a metal precursor. The metal precursor includes a metal, and the polymerizable composition includes a multiplicity of multifunctional components. Each multifunctional component includes a reactive moiety extending from a surface of the substrate to form a reactive surface. An interface between the reactive surface and the aqueous solution is selectively irradiated to form nanoparticles including the metal in a desired pattern. The nanoparticles are chemically coupled to the reactive surface by reactive moieties, thereby forming a metallic layer on the surface of the substrate.

Abstract: A package assembly includes a package substrate, a solder resist layer on the package substrate and including an elongated solder resist opening, and an interposer module on the package substrate and including a corner located on the elongated solder resist opening.

Abstract: In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.

Abstract: A package structure includes a circuit substrate, a semiconductor package, a thermal interface material, a lid structure and a heat dissipation structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The thermal interface material is disposed on the semiconductor package. The lid structure is disposed on the circuit substrate and surrounding the semiconductor package, wherein the lid structure comprises a supporting part that is partially covering and in physical contact with the thermal interface material. The heat dissipation structure is disposed on the lid structure and in physical contact with the supporting part of the lid structure.

Abstract: This disclosure relates to picolinamides of Formula I and their use as fungicides.

Abstract: A package assembly includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and attached to the package substrate. The package lid includes an outer lid including an outer lid material and including an outer lid plate portion. The package lid further includes an inner lid including an inner lid material different than the outer lid material and including an inner lid plate portion attached to a bottom surface of the outer lid plate portion.

Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Abstract: Example computer-implemented methods, media, and systems for processing input/output (I/O) commands using block size aware polling are disclosed. One example method includes creating multiple polling queues and multiple interrupt queues in a transport drivers layer of a storage stack. A first I/O command is received from a core layer of the storage stack and by the transport drivers layer. A ratio of a total number of multiple small block size commands in the transport drivers layer to a total number of multiple outstanding I/O commands in the transport drivers layer is determined to be larger than a predetermined first threshold. In response to determining that the ratio is larger than the predetermined first threshold, the polling mode is applied to the first I/O command through the submission of the first I/O command to a first polling queue in the multiple polling queues.

Abstract: A boron layer may be formed as a passivation layer in a recess in which a deep trench isolation structure (DTI) structure is to be formed. The boron layer results in formation of a boron-silicon interface between the DTI structure and a photodiode of a pixel sensor included in a pixel array. The boron-silicon interface functions as a diode junction, which resists penetration of photons into the DTI structure. This reduces and/or minimizes photon transmission through the DTI structure, which reduces and/or minimizes optical crosstalk between pixel sensors of the pixel array.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

Abstract: Disclosed are a storage device and method, an electronic device, and a storage medium. The device includes: a first splitting logical module for splitting a first access command into at least two second access commands based on an access address of the first access command; and at least two storage array modules, each of which is configured to perform a corresponding access operation based on one of the at least two second access commands of the first splitting logical module. According to the embodiments, the first access command with relatively long burst is split into second access commands with smaller granularity, and the at least two storage array modules are parallel accessed, whereby the at least two storage array modules can respond in parallel, effectively reducing response time of the first access command and access time of each master when parallel access of masters exists, then improving access efficiency.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.