Patents by Inventor Yu Yao

Yu Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240083918
    Abstract: Disclosed are compounds of Formula (I), methods of using the compounds for inhibiting ALK2 activity and pharmaceutical compositions comprising such compounds. The compounds are useful in treating, preventing or ameliorating diseases or disorders associated with ALK2 activity such as cancer.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 14, 2024
    Inventors: Jun Pan, Yu Bai, Liangxing Wu, Wenqing Yao
  • Publication number: 20240082640
    Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240087974
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240085808
    Abstract: A particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. The processing chamber is configured to perform a lithography exposure process on a semiconductor wafer. The method also includes fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle, attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer, and loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. The method also includes loading the semiconductor wafer into the processing chamber, and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder after the cleaning cycle.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Yuan YAO, Yu-Yu CHEN, Hsiang-Lung TSOU
  • Publication number: 20240084028
    Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.
    Type: Application
    Filed: March 13, 2023
    Publication date: March 14, 2024
    Inventors: Rong-Hwa LIN, Shih-Yao LIN, Yu-Ying TSAI
  • Publication number: 20240082642
    Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240088063
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Publication number: 20240089607
    Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.
    Type: Application
    Filed: May 29, 2023
    Publication date: March 14, 2024
    Applicant: HTC Corporation
    Inventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
  • Patent number: 11927991
    Abstract: Embodiments of synchronized hinges for foldable displays are described. In some embodiments, a hinge may include: a first bracket coupled to a first shaft via a first arm, a second bracket coupled to a second shaft via a second arm, and a synchronization bracket coupled to the first and second shafts.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Dell Products, L.P.
    Inventors: Christopher A. Torres, Enoch Chen, Anthony J. Sanchez, Chia-Hao Hsu, Hsu Hong Yao, Mo-Yu Zhang
  • Patent number: 11923384
    Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a first transistor. The first transistor includes a first semiconductor layer, and the first semiconductor layer includes bismuth selenium oxide materials to enhance mobility of the first transistor and improve electrical performance of the display panel, so that the display panel meets requirements of high refresh rate and high transmittance.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 5, 2024
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yu Zhang, Miao Jiang, Jiangbo Yao, Lixuan Chen, Xin Zhang
  • Publication number: 20240074062
    Abstract: An electronic device is provided, including an electronic element, and a protective substrate. The protective substrate includes a concave portion, and a flat portion. The concave portion has a concave surface and a convex surface that is opposite to the concave surface. The flat portion is connected to the concave portion. The electronic element overlaps the concave portion and is arranged under the convex surface.
    Type: Application
    Filed: July 20, 2023
    Publication date: February 29, 2024
    Inventors: Hsin-Fa HSU, Yu-Ling HUNG, Hsien-Yao HSIAO, Tsu-Hsien KU
  • Patent number: 11915991
    Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Patent number: 11893000
    Abstract: This specification provides data processing methods, apparatuses and devices. In embodiments of the specification, table data includes a state identifier for indicating whether a target table is in a use state or an idle state. Therefore, after an occupying-table request is received, the table data can be obtained, and the state of the target table can be determined from the state identifier in the table data. If the target table is in the idle state, the table data is locked; after the state identifier is updated to the use state, the table data is released; and occupying-table data of the target table is generated to respond to the occupying-table request.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 6, 2024
    Assignee: ZHEJIANG KOUBEI NETWORK TECHNOLOGY CO., LTD.
    Inventors: Yu Yao, Dafeng Wang
  • Publication number: 20240014332
    Abstract: Provided is a method for making an electrode of a photovoltaic cell. The method includes the following steps: a mask material is deposited over the side and at least one surface of a photovoltaic device, where the mask material layer is divided into body part and opening part; the opening part is patterned to form a local opening; metal is electrochemically deposited in the local opening to form an electrode; and the body part is removed.
    Type: Application
    Filed: September 1, 2023
    Publication date: January 11, 2024
    Inventors: Yu Yao, Zhongtian Li
  • Publication number: 20230406304
    Abstract: A method for training a deep-learning-based machine learning algorithm. The method includes: providing training data for training the deep-learning-based machine learning algorithm, wherein the training data comprise sensor data; training, by a machine learning method, the deep-learning-based machine learning algorithm based on the training data; and subsequently optimizing at least one parameter of the trained deep-learning-based machine learning algorithm based on a non-differentiable cost function.
    Type: Application
    Filed: April 7, 2023
    Publication date: December 21, 2023
    Inventors: Amulya Hiremath, Barbara Rakitsch, Gonca Guersun, Joerg Wagner, Michael Herman, Nils Oliver Ferguson, Rahul Pandey, Yu Yao
  • Publication number: 20230405918
    Abstract: An additive manufacturing process for forming a metallic layer on the surface of the substrate includes fabricating a substrate from a polymerizable composition by a stereolithographic process, and contacting the reactive surface with an aqueous solution including a metal precursor. The metal precursor includes a metal, and the polymerizable composition includes a multiplicity of multifunctional components. Each multifunctional component includes a reactive moiety extending from a surface of the substrate to form a reactive surface. An interface between the reactive surface and the aqueous solution is selectively irradiated to form nanoparticles including the metal in a desired pattern. The nanoparticles are chemically coupled to the reactive surface by reactive moieties, thereby forming a metallic layer on the surface of the substrate.
    Type: Application
    Filed: July 27, 2023
    Publication date: December 21, 2023
    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Zhi Zhao, Chao Wang, Yu Yao
  • Publication number: 20230411425
    Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 21, 2023
    Inventors: Yu-Hung Cheng, Ching I Li, Yu-Siang Fang, Yu-Yao Hsia, Min-Ying Tsai
  • Patent number: 11843350
    Abstract: Provided herein are systems and related methods of performing solar field and receiver inspections based on polarimetric-enhanced imaging.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: December 12, 2023
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Yu Yao, Chao Wang, Julius Yellowhair, Jing Bai, Jiawei Zuo
  • Patent number: 11826946
    Abstract: An additive manufacturing process for forming a metallic layer on the surface of the substrate includes fabricating a substrate from a polymerizable composition by a stereolithographic process, and contacting the reactive surface with an aqueous solution including a metal precursor. The metal precursor includes a metal, and the polymerizable composition includes a multiplicity of multifunctional components. Each multifunctional component includes a reactive moiety extending from a surface of the substrate to form a reactive surface. An interface between the reactive surface and the aqueous solution is selectively irradiated to form nanoparticles including the metal in a desired pattern. The nanoparticles are chemically coupled to the reactive surface by reactive moieties, thereby forming a metallic layer on the surface of the substrate.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 28, 2023
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Zhi Zhao, Chao Wang, Yu Yao